Support debug system bus access.

[riscv-isa-sim.git] / riscv / trap.cc

diff --git a/riscv/trap.cc b/riscv/trap.cc
index ead3a0047c6cdab0abe24121007da8791e3417f6..4ac2f1f717423ca0ba133840b54abfcfb37c0a3e 100644 (file)
--- a/riscv/trap.cc
+++ b/riscv/trap.cc
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #include "trap.h"
 #include "processor.h"
 #include <cstdio>
@@ -8,8 +10,3 @@ const char* trap_t::name()
   sprintf(_name, fmt, uint8_t(which));
   return _name;
 }
-
-void mem_trap_t::side_effects(state_t* state)
-{
-  state->badvaddr = badvaddr;
-}