Set tval to 0 on traps with no specified tval

[riscv-isa-sim.git] / riscv / trap.h

diff --git a/riscv/trap.h b/riscv/trap.h
index a289a6842af5aff0c5782e175a7f6331eac33605..1fe44eb08d6aea33aab49d631fc8c167a5a6f4cb 100644 (file)
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -14,7 +14,7 @@ class trap_t
   trap_t(reg_t which) : which(which) {}
   virtual const char* name();
   virtual bool has_badaddr() { return false; }
-  virtual reg_t get_badaddr() { abort(); }
+  virtual reg_t get_badaddr() { return 0; }
   reg_t cause() { return which; }
  private:
   char _name[16];
@@ -46,8 +46,8 @@ class mem_trap_t : public trap_t
 
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault)
-DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction)
-DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint)
+DECLARE_MEM_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction)
+DECLARE_MEM_TRAP(CAUSE_BREAKPOINT, breakpoint)
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_LOAD_ACCESS, load_access_fault)