add BSD license

[riscv-isa-sim.git] / riscv / trap.h

diff --git a/riscv/trap.h b/riscv/trap.h
index 61b44360f6cb139828be09152d28ee0fecf593e6..6448e51cf67a061a190500bead2d79af707cd1a4 100644 (file)
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #ifndef _RISCV_TRAP_H
 #define _RISCV_TRAP_H
 
@@ -7,26 +9,17 @@
   DECLARE_TRAP(illegal_instruction), \
   DECLARE_TRAP(privileged_instruction), \
   DECLARE_TRAP(fp_disabled), \
-  DECLARE_TRAP(interrupt), \
+  DECLARE_TRAP(reserved0), \
   DECLARE_TRAP(syscall), \
   DECLARE_TRAP(breakpoint), \
-  DECLARE_TRAP(data_address_misaligned), \
+  DECLARE_TRAP(load_address_misaligned), \
+  DECLARE_TRAP(store_address_misaligned), \
   DECLARE_TRAP(load_access_fault), \
   DECLARE_TRAP(store_access_fault), \
+  DECLARE_TRAP(vector_disabled), \
+  DECLARE_TRAP(vector_bank), \
+  DECLARE_TRAP(vector_illegal_instruction), \
   DECLARE_TRAP(reserved1), \
-  DECLARE_TRAP(reserved2), \
-  DECLARE_TRAP(reserved3), \
-  DECLARE_TRAP(reserved4), \
-  DECLARE_TRAP(reserved5), \
-  DECLARE_TRAP(reserved6), \
-  DECLARE_TRAP(int0), \
-  DECLARE_TRAP(int1), \
-  DECLARE_TRAP(int2), \
-  DECLARE_TRAP(int3), \
-  DECLARE_TRAP(int4), \
-  DECLARE_TRAP(int5), \
-  DECLARE_TRAP(int6), \
-  DECLARE_TRAP(int7), \
 
 #define DECLARE_TRAP(x) trap_##x
 enum trap_t
@@ -34,6 +27,10 @@ enum trap_t
   TRAP_LIST
   NUM_TRAPS
 };
+#undef DECLARE_TRAP
+
+struct interrupt_t { interrupt_t(int which) : i(which) {} int i; };
+struct halt_t {}; // thrown to stop the processor from running
 
 extern "C" const char* trap_name(trap_t t);