Support setting ISA/subsets with --isa flag

[riscv-isa-sim.git] / spike_main / disasm.cc

diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc
index 10bd20481c8c32e24917379ea087c46d0f52625e..275fb561ccf518b91711b445a1e9f505e334f1f8 100644 (file)
--- a/spike_main/disasm.cc
+++ b/spike_main/disasm.cc
@@ -120,6 +120,94 @@ struct : public arg_t {
   }
 } jump_target;
 
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return xpr_name[insn.rvc_rs1()];
+  }
+} rvc_rs1;
+
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return xpr_name[insn.rvc_rds()];
+  }
+} rvc_rds;
+
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return xpr_name[insn.rvc_rs1s()];
+  }
+} rvc_rs1s;
+
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return std::to_string((int)insn.rvc_imm());
+  }
+} rvc_imm;
+
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return std::to_string((int)insn.rvc_lwsp_imm());
+  }
+} rvc_lwsp_imm;
+
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return std::to_string((int)(insn.rvc_imm() & 0x3f));
+  }
+} rvc_shamt;
+
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    std::stringstream s;
+    s << std::hex << "0x" << (uint32_t)insn.rvc_imm();
+    return s.str();
+  }
+} rvc_uimm;
+
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return std::to_string((int)insn.rvc_lwsp_imm()) + '(' + xpr_name[2] + ')';
+  }
+} rvc_lwsp_address;
+
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return std::to_string((int)insn.rvc_ldsp_imm()) + '(' + xpr_name[2] + ')';
+  }
+} rvc_ldsp_address;
+
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return std::to_string((int)insn.rvc_lw_imm()) + '(' + xpr_name[insn.rvc_rs1s()] + ')';
+  }
+} rvc_lw_address;
+
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return std::to_string((int)insn.rvc_ld_imm()) + '(' + xpr_name[insn.rvc_rs1s()] + ')';
+  }
+} rvc_ld_address;
+
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    std::stringstream s;
+    int32_t target = insn.rvc_b_imm();
+    char sign = target >= 0 ? '+' : '-';
+    s << "pc " << sign << ' ' << abs(target);
+    return s.str();
+  }
+} rvc_branch_target;
+
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    std::stringstream s;
+    int32_t target = insn.rvc_j_imm();
+    char sign = target >= 0 ? '+' : '-';
+    s << "pc " << sign << ' ' << abs(target);
+    return s.str();
+  }
+} rvc_jump_target;
+
 std::string disassembler_t::disassemble(insn_t insn)
 {
   const disasm_insn_t* disasm_insn = lookup(insn);
@@ -132,8 +220,11 @@ disassembler_t::disassembler_t()
   const uint32_t match_rd_ra = 1UL << 7;
   const uint32_t mask_rs1 = 0x1fUL << 15;
   const uint32_t match_rs1_ra = 1UL << 15;
+  const uint32_t mask_rvc_rs1 = 0x1fUL << 2;
+  const uint32_t match_rvc_rs1_ra = 1UL << 2;
   const uint32_t mask_rs2 = 0x1fUL << 20;
   const uint32_t mask_imm = 0xfffUL << 20;
+  const uint32_t match_imm_1 = 1UL << 20;
 
   #define DECLARE_INSN(code, match, mask) \
    const uint32_t match_##code = match; \
@@ -213,7 +304,6 @@ disassembler_t::disassembler_t()
   add_insn(new disasm_insn_t("jal", match_jal | match_rd_ra, mask_jal | mask_rd, {&jump_target}));
   add_insn(new disasm_insn_t("jal", match_jal, mask_jal, {&xrd, &jump_target}));
 
-  DEFINE_B0TYPE("b",    beq);
   DEFINE_B1TYPE("beqz", beq);
   DEFINE_B1TYPE("bnez", bne);
   DEFINE_B1TYPE("bltz", blt);
@@ -236,16 +326,19 @@ disassembler_t::disassembler_t()
   add_insn(new disasm_insn_t("nop", match_addi, mask_addi | mask_rd | mask_rs1 | mask_imm, {}));
   add_insn(new disasm_insn_t(" - ", match_xor, mask_xor | mask_rd | mask_rs1 | mask_rs2, {})); // for machine-generated bubbles
   DEFINE_I0TYPE("li", addi);
-  DEFINE_I1TYPE("move", addi);
+  DEFINE_I1TYPE("mv", addi);
   DEFINE_ITYPE(addi);
   DEFINE_ITYPE(slli);
   DEFINE_ITYPE(slti);
+  add_insn(new disasm_insn_t("seqz", match_sltiu | match_imm_1, mask_sltiu | mask_imm, {&xrd, &xrs1}));
   DEFINE_ITYPE(sltiu);
+  add_insn(new disasm_insn_t("not", match_xori | mask_imm, mask_xori | mask_imm, {&xrd, &xrs1}));
   DEFINE_ITYPE(xori);
   DEFINE_ITYPE(srli);
   DEFINE_ITYPE(srai);
   DEFINE_ITYPE(ori);
   DEFINE_ITYPE(andi);
+  DEFINE_I1TYPE("sext.w", addiw);
   DEFINE_ITYPE(addiw);
   DEFINE_ITYPE(slliw);
   DEFINE_ITYPE(srliw);
@@ -255,6 +348,7 @@ disassembler_t::disassembler_t()
   DEFINE_RTYPE(sub);
   DEFINE_RTYPE(sll);
   DEFINE_RTYPE(slt);
+  add_insn(new disasm_insn_t("snez", match_sltu, mask_sltu | mask_rs1, {&xrd, &xrs2}));
   DEFINE_RTYPE(sltu);
   DEFINE_RTYPE(xor);
   DEFINE_RTYPE(srl);
@@ -287,6 +381,11 @@ disassembler_t::disassembler_t()
 
   add_insn(new disasm_insn_t("csrr", match_csrrs, mask_csrrs | mask_rs1, {&xrd, &csr}));
   add_insn(new disasm_insn_t("csrw", match_csrrw, mask_csrrw | mask_rd, {&csr, &xrs1}));
+  add_insn(new disasm_insn_t("csrs", match_csrrs, mask_csrrs | mask_rd, {&csr, &xrs1}));
+  add_insn(new disasm_insn_t("csrc", match_csrrc, mask_csrrc | mask_rd, {&csr, &xrs1}));
+  add_insn(new disasm_insn_t("csrwi", match_csrrwi, mask_csrrwi | mask_rd, {&csr, &zimm5}));
+  add_insn(new disasm_insn_t("csrsi", match_csrrsi, mask_csrrsi | mask_rd, {&csr, &zimm5}));
+  add_insn(new disasm_insn_t("csrci", match_csrrci, mask_csrrci | mask_rd, {&csr, &zimm5}));
   add_insn(new disasm_insn_t("csrrw", match_csrrw, mask_csrrw, {&xrd, &csr, &xrs1}));
   add_insn(new disasm_insn_t("csrrs", match_csrrs, mask_csrrs, {&xrd, &csr, &xrs1}));
   add_insn(new disasm_insn_t("csrrc", match_csrrc, mask_csrrc, {&xrd, &csr, &xrs1}));
@@ -357,6 +456,31 @@ disassembler_t::disassembler_t()
   DEFINE_FXTYPE(flt_d);
   DEFINE_FXTYPE(fle_d);
 
+  add_insn(new disasm_insn_t("sbreak", match_c_li | 0x1000, 0xffff, {}));
+  DISASM_INSN("li", c_li, 0, {&xrd, &rvc_imm});
+  DISASM_INSN("lui", c_lui, 0, {&xrd, &rvc_uimm});
+  DISASM_INSN("addi", c_addi, 0, {&xrd, &xrd, &rvc_imm});
+  DISASM_INSN("addiw", c_addiw, 0, {&xrd, &xrd, &rvc_imm});
+  DISASM_INSN("slli", c_slli, 0, {&xrd, &rvc_shamt});
+  DISASM_INSN("addi", c_addi4, 0, {&xrd, &xrd, &rvc_lwsp_imm});
+  DISASM_INSN("mv", c_mv, 0, {&xrd, &rvc_rs1});
+  add_insn(new disasm_insn_t("ret", match_c_jalr | match_rvc_rs1_ra, mask_c_jalr | mask_rd | mask_rvc_rs1, {}));
+  DISASM_INSN("jr", c_jalr, mask_rd, {&xrd, &rvc_rs1});
+  DISASM_INSN("jalr", c_jalr, mask_rd, {&xrd, &rvc_rs1});
+  DISASM_INSN("add", c_add, 0, {&xrd, &xrd, &rvc_rs1});
+  DISASM_INSN("addw", c_addw, 0, {&xrd, &xrd, &rvc_rs1});
+  DISASM_INSN("lw", c_lwsp, 0, {&xrd, &rvc_lwsp_address});
+  DISASM_INSN("ld", c_ldsp, 0, {&xrd, &rvc_ldsp_address});
+  DISASM_INSN("sw", c_swsp, 0, {&xrd, &rvc_lwsp_address});
+  DISASM_INSN("sd", c_sdsp, 0, {&xrd, &rvc_ldsp_address});
+  DISASM_INSN("lw", c_lw, 0, {&rvc_rds, &rvc_lw_address});
+  DISASM_INSN("ld", c_ld, 0, {&rvc_rds, &rvc_ld_address});
+  DISASM_INSN("sw", c_sw, 0, {&rvc_rds, &rvc_lw_address});
+  DISASM_INSN("sd", c_sd, 0, {&rvc_rds, &rvc_ld_address});
+  DISASM_INSN("beqz", c_beqz, 0, {&rvc_rds, &rvc_branch_target});
+  DISASM_INSN("bnez", c_bnez, 0, {&rvc_rds, &rvc_branch_target});
+  DISASM_INSN("j", c_j, 0, {&rvc_jump_target});
+
   // provide a default disassembly for all instructions as a fallback
   #define DECLARE_INSN(code, match, mask) \
    add_insn(new disasm_insn_t(#code " (args unknown)", match, mask, {}));