Support for non-contiguous hartids

[riscv-isa-sim.git] / spike_main / disasm.cc

diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc
index 51283a3f9cc25142b264ea40ac05f12c01ddc4c9..eedc6b8bc54e6b00dc9986b50d59a725a5249666 100644 (file)
--- a/spike_main/disasm.cc
+++ b/spike_main/disasm.cc
@@ -7,7 +7,6 @@
 #include <sstream>
 #include <stdlib.h>
 
-
 struct : public arg_t {
   std::string to_string(insn_t insn) const {
     return std::to_string((int)insn.i_imm()) + '(' + xpr_name[insn.rs1()] + ')';
@@ -75,7 +74,12 @@ struct : public arg_t {
       #define DECLARE_CSR(name, num) case num: return #name;
       #include "encoding.h"
       #undef DECLARE_CSR
-      default: return "unknown";
+      default:
+      {
+        char buf[16];
+        snprintf(buf, sizeof buf, "unknown_%03" PRIx64, insn.csr());
+        return std::string(buf);
+      }
     }
   }
 } csr;
@@ -244,13 +248,13 @@ struct : public arg_t {
   }
 } rvc_jump_target;
 
-std::string disassembler_t::disassemble(insn_t insn)
+std::string disassembler_t::disassemble(insn_t insn) const
 {
   const disasm_insn_t* disasm_insn = lookup(insn);
   return disasm_insn ? disasm_insn->to_string(insn) : "unknown";
 }
 
-disassembler_t::disassembler_t()
+disassembler_t::disassembler_t(int xlen)
 {
   const uint32_t mask_rd = 0x1fUL << 7;
   const uint32_t match_rd_ra = 1UL << 7;
@@ -410,8 +414,11 @@ disassembler_t::disassembler_t()
   DEFINE_RTYPE(remw);
   DEFINE_RTYPE(remuw);
 
-  DEFINE_NOARG(scall);
-  DEFINE_NOARG(sbreak);
+  DEFINE_NOARG(ecall);
+  DEFINE_NOARG(ebreak);
+  DEFINE_NOARG(uret);
+  DEFINE_NOARG(sret);
+  DEFINE_NOARG(mret);
   DEFINE_NOARG(fence);
   DEFINE_NOARG(fence_i);
 
@@ -428,7 +435,6 @@ disassembler_t::disassembler_t()
   add_insn(new disasm_insn_t("csrrwi", match_csrrwi, mask_csrrwi, {&xrd, &csr, &zimm5}));
   add_insn(new disasm_insn_t("csrrsi", match_csrrsi, mask_csrrsi, {&xrd, &csr, &zimm5}));
   add_insn(new disasm_insn_t("csrrci", match_csrrci, mask_csrrci, {&xrd, &csr, &zimm5}));
-  DEFINE_NOARG(sret)
 
   DEFINE_FRTYPE(fadd_s);
   DEFINE_FRTYPE(fsub_s);
@@ -450,13 +456,13 @@ disassembler_t::disassembler_t()
   DEFINE_XFTYPE(fcvt_s_w);
   DEFINE_XFTYPE(fcvt_s_wu);
   DEFINE_XFTYPE(fcvt_s_wu);
-  DEFINE_XFTYPE(fmv_s_x);
+  DEFINE_XFTYPE(fmv_w_x);
   DEFINE_FXTYPE(fcvt_l_s);
   DEFINE_FXTYPE(fcvt_lu_s);
   DEFINE_FXTYPE(fcvt_w_s);
   DEFINE_FXTYPE(fcvt_wu_s);
   DEFINE_FXTYPE(fclass_s);
-  DEFINE_FXTYPE(fmv_x_s);
+  DEFINE_FXTYPE(fmv_x_w);
   DEFINE_FXTYPE(feq_s);
   DEFINE_FXTYPE(flt_s);
   DEFINE_FXTYPE(fle_s);
@@ -494,15 +500,14 @@ disassembler_t::disassembler_t()
 
   DISASM_INSN("ebreak", c_add, mask_rd | mask_rvc_rs2, {});
   add_insn(new disasm_insn_t("ret", match_c_li | match_rd_ra, mask_c_li | mask_rd | mask_rvc_imm, {}));
-  DISASM_INSN("jr", c_li, mask_rvc_imm, {&rvc_rs1});
-  DISASM_INSN("jalr", c_lui, mask_rvc_imm, {&rvc_rs1});
+  DISASM_INSN("jr", c_jr, mask_rvc_imm, {&rvc_rs1});
+  DISASM_INSN("jalr", c_jalr, mask_rvc_imm, {&rvc_rs1});
   DISASM_INSN("nop", c_addi, mask_rd | mask_rvc_imm, {});
   DISASM_INSN("addi", c_addi16sp, mask_rd, {&rvc_sp, &rvc_sp, &rvc_addi16sp_imm});
   DISASM_INSN("addi", c_addi4spn, 0, {&rvc_rs1s, &rvc_sp, &rvc_addi4spn_imm});
   DISASM_INSN("li", c_li, 0, {&xrd, &rvc_imm});
   DISASM_INSN("lui", c_lui, 0, {&xrd, &rvc_uimm});
   DISASM_INSN("addi", c_addi, 0, {&xrd, &xrd, &rvc_imm});
-  DISASM_INSN("addiw", c_addiw, 0, {&xrd, &xrd, &rvc_imm});
   DISASM_INSN("slli", c_slli, 0, {&xrd, &rvc_shamt});
   DISASM_INSN("mv", c_mv, 0, {&xrd, &rvc_rs2});
   DISASM_INSN("add", c_add, 0, {&xrd, &xrd, &rvc_rs2});
@@ -513,17 +518,28 @@ disassembler_t::disassembler_t()
   DISASM_INSN("or", c_or, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s});
   DISASM_INSN("xor", c_xor, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s});
   DISASM_INSN("lw", c_lwsp, 0, {&xrd, &rvc_lwsp_address});
-  DISASM_INSN("flw", c_flwsp, 0, {&xrd, &rvc_lwsp_address});
+  DISASM_INSN("fld", c_fld, 0, {&rvc_rs2s, &rvc_ld_address});
   DISASM_INSN("sw", c_swsp, 0, {&rvc_rs2, &rvc_swsp_address});
-  DISASM_INSN("fsw", c_fswsp, 0, {&rvc_rs2, &rvc_swsp_address});
   DISASM_INSN("lw", c_lw, 0, {&rvc_rs2s, &rvc_lw_address});
-  DISASM_INSN("flw", c_flw, 0, {&rvc_rs2s, &rvc_lw_address});
   DISASM_INSN("sw", c_sw, 0, {&rvc_rs2s, &rvc_lw_address});
-  DISASM_INSN("fsw", c_fsw, 0, {&rvc_rs2s, &rvc_lw_address});
   DISASM_INSN("beqz", c_beqz, 0, {&rvc_rs1s, &rvc_branch_target});
   DISASM_INSN("bnez", c_bnez, 0, {&rvc_rs1s, &rvc_branch_target});
   DISASM_INSN("j", c_j, 0, {&rvc_jump_target});
 
+  if (xlen == 32) {
+    DISASM_INSN("flw", c_flw, 0, {&rvc_rs2s, &rvc_lw_address});
+    DISASM_INSN("flw", c_flwsp, 0, {&xrd, &rvc_lwsp_address});
+    DISASM_INSN("fsw", c_fsw, 0, {&rvc_rs2s, &rvc_lw_address});
+    DISASM_INSN("fsw", c_fswsp, 0, {&rvc_rs2, &rvc_swsp_address});
+    DISASM_INSN("jal", c_jal, 0, {&rvc_jump_target});
+  } else {
+    DISASM_INSN("ld", c_ld, 0, {&rvc_rs2s, &rvc_ld_address});
+    DISASM_INSN("ld", c_ldsp, 0, {&xrd, &rvc_ldsp_address});
+    DISASM_INSN("sd", c_sd, 0, {&rvc_rs2s, &rvc_ld_address});
+    DISASM_INSN("sd", c_sdsp, 0, {&rvc_rs2, &rvc_sdsp_address});
+    DISASM_INSN("addiw", c_addiw, 0, {&xrd, &xrd, &rvc_imm});
+  }
+
   // provide a default disassembly for all instructions as a fallback
   #define DECLARE_INSN(code, match, mask) \
    add_insn(new disasm_insn_t(#code " (args unknown)", match, mask, {}));
@@ -531,7 +547,7 @@ disassembler_t::disassembler_t()
   #undef DECLARE_INSN
 }
 
-const disasm_insn_t* disassembler_t::lookup(insn_t insn)
+const disasm_insn_t* disassembler_t::lookup(insn_t insn) const
 {
   size_t idx = insn.bits() % HASH_SIZE;
   for (size_t j = 0; j < chain[idx].size(); j++)