Allow configuration of default ISA with --with-isa

[riscv-isa-sim.git] / spike_main / spike.cc

diff --git a/spike_main/spike.cc b/spike_main/spike.cc
index 13983a00486aa43f6e150a123ba8026384276fb0..4f8f42dc357f00cc416231ce1c9ff0af4f39c8b7 100644 (file)
--- a/spike_main/spike.cc
+++ b/spike_main/spike.cc
@@ -17,13 +17,13 @@ static void help()
 {
   fprintf(stderr, "usage: spike [host options] <target program> [target options]\n");
   fprintf(stderr, "Host Options:\n");
-  fprintf(stderr, "  -p <n>             Simulate <n> processors [default 1]\n");
-  fprintf(stderr, "  -m <n>             Provide <n> MiB of target memory [default 4096]\n");
+  fprintf(stderr, "  -p<n>              Simulate <n> processors [default 1]\n");
+  fprintf(stderr, "  -m<n>              Provide <n> MiB of target memory [default 4096]\n");
   fprintf(stderr, "  -d                 Interactive debug mode\n");
   fprintf(stderr, "  -g                 Track histogram of PCs\n");
   fprintf(stderr, "  -l                 Generate a log of execution\n");
   fprintf(stderr, "  -h                 Print this help message\n");
-  fprintf(stderr, "  --isa=<name>       RISC-V ISA string [default RV64IMAFDC]\n");
+  fprintf(stderr, "  --isa=<name>       RISC-V ISA string [default %s]\n", DEFAULT_ISA);
   fprintf(stderr, "  --ic=<S>:<W>:<B>   Instantiate a cache model with S sets,\n");
   fprintf(stderr, "  --dc=<S>:<W>:<B>     W ways, and B-byte blocks (with S and\n");
   fprintf(stderr, "  --l2=<S>:<W>:<B>     B both powers of 2).\n");
@@ -43,7 +43,7 @@ int main(int argc, char** argv)
   std::unique_ptr<dcache_sim_t> dc;
   std::unique_ptr<cache_sim_t> l2;
   std::function<extension_t*()> extension;
-  const char* isa = "RV64";
+  const char* isa = DEFAULT_ISA;
 
   option_parser_t parser;
   parser.help(&help);