{
fprintf(stderr, "usage: spike [host options] <target program> [target options]\n");
fprintf(stderr, "Host Options:\n");
- fprintf(stderr, " -p <n> Simulate <n> processors [default 1]\n");
- fprintf(stderr, " -m <n> Provide <n> MiB of target memory [default 4096]\n");
+ fprintf(stderr, " -p<n> Simulate <n> processors [default 1]\n");
+ fprintf(stderr, " -m<n> Provide <n> MiB of target memory [default 4096]\n");
fprintf(stderr, " -d Interactive debug mode\n");
fprintf(stderr, " -g Track histogram of PCs\n");
+ fprintf(stderr, " -l Generate a log of execution\n");
fprintf(stderr, " -h Print this help message\n");
- fprintf(stderr, " --isa=<name> RISC-V ISA string [default RV64IMAFDC]\n");
+ fprintf(stderr, " --isa=<name> RISC-V ISA string [default %s]\n", DEFAULT_ISA);
fprintf(stderr, " --ic=<S>:<W>:<B> Instantiate a cache model with S sets,\n");
fprintf(stderr, " --dc=<S>:<W>:<B> W ways, and B-byte blocks (with S and\n");
fprintf(stderr, " --l2=<S>:<W>:<B> B both powers of 2).\n");
{
bool debug = false;
bool histogram = false;
+ bool log = false;
size_t nprocs = 1;
size_t mem_mb = 0;
std::unique_ptr<icache_sim_t> ic;
std::unique_ptr<dcache_sim_t> dc;
std::unique_ptr<cache_sim_t> l2;
std::function<extension_t*()> extension;
- const char* isa = "RV64";
+ const char* isa = DEFAULT_ISA;
option_parser_t parser;
parser.help(&help);
parser.option('h', 0, 0, [&](const char* s){help();});
parser.option('d', 0, 0, [&](const char* s){debug = true;});
parser.option('g', 0, 0, [&](const char* s){histogram = true;});
+ parser.option('l', 0, 0, [&](const char* s){log = true;});
parser.option('p', 0, 1, [&](const char* s){nprocs = atoi(s);});
parser.option('m', 0, 1, [&](const char* s){mem_mb = atoi(s);});
parser.option(0, "ic", 1, [&](const char* s){ic.reset(new icache_sim_t(s));});
}
s.set_debug(debug);
+ s.set_log(log);
s.set_histogram(histogram);
return s.run();
}