Split ERET into URET, SRET, HRET, MRET

[riscv-isa-sim.git] / spike_main / spike.cc

diff --git a/spike_main/spike.cc b/spike_main/spike.cc
index ab5cea554957a97e388e7d71e351c94f8bffb332..4f8f42dc357f00cc416231ce1c9ff0af4f39c8b7 100644 (file)
--- a/spike_main/spike.cc
+++ b/spike_main/spike.cc
@@ -17,11 +17,13 @@ static void help()
 {
   fprintf(stderr, "usage: spike [host options] <target program> [target options]\n");
   fprintf(stderr, "Host Options:\n");
-  fprintf(stderr, "  -p <n>             Simulate <n> processors\n");
-  fprintf(stderr, "  -m <n>             Provide <n> MB of target memory\n");
+  fprintf(stderr, "  -p<n>              Simulate <n> processors [default 1]\n");
+  fprintf(stderr, "  -m<n>              Provide <n> MiB of target memory [default 4096]\n");
   fprintf(stderr, "  -d                 Interactive debug mode\n");
   fprintf(stderr, "  -g                 Track histogram of PCs\n");
+  fprintf(stderr, "  -l                 Generate a log of execution\n");
   fprintf(stderr, "  -h                 Print this help message\n");
+  fprintf(stderr, "  --isa=<name>       RISC-V ISA string [default %s]\n", DEFAULT_ISA);
   fprintf(stderr, "  --ic=<S>:<W>:<B>   Instantiate a cache model with S sets,\n");
   fprintf(stderr, "  --dc=<S>:<W>:<B>     W ways, and B-byte blocks (with S and\n");
   fprintf(stderr, "  --l2=<S>:<W>:<B>     B both powers of 2).\n");
@@ -34,23 +36,27 @@ int main(int argc, char** argv)
 {
   bool debug = false;
   bool histogram = false;
+  bool log = false;
   size_t nprocs = 1;
   size_t mem_mb = 0;
   std::unique_ptr<icache_sim_t> ic;
   std::unique_ptr<dcache_sim_t> dc;
   std::unique_ptr<cache_sim_t> l2;
   std::function<extension_t*()> extension;
+  const char* isa = DEFAULT_ISA;
 
   option_parser_t parser;
   parser.help(&help);
   parser.option('h', 0, 0, [&](const char* s){help();});
   parser.option('d', 0, 0, [&](const char* s){debug = true;});
   parser.option('g', 0, 0, [&](const char* s){histogram = true;});
+  parser.option('l', 0, 0, [&](const char* s){log = true;});
   parser.option('p', 0, 1, [&](const char* s){nprocs = atoi(s);});
   parser.option('m', 0, 1, [&](const char* s){mem_mb = atoi(s);});
   parser.option(0, "ic", 1, [&](const char* s){ic.reset(new icache_sim_t(s));});
   parser.option(0, "dc", 1, [&](const char* s){dc.reset(new dcache_sim_t(s));});
   parser.option(0, "l2", 1, [&](const char* s){l2.reset(cache_sim_t::construct(s, "L2$"));});
+  parser.option(0, "isa", 1, [&](const char* s){isa = s;});
   parser.option(0, "extension", 1, [&](const char* s){extension = find_extension(s);});
   parser.option(0, "extlib", 1, [&](const char *s){
     void *lib = dlopen(s, RTLD_NOW | RTLD_GLOBAL);
@@ -64,7 +70,7 @@ int main(int argc, char** argv)
   if (!*argv1)
     help();
   std::vector<std::string> htif_args(argv1, (const char*const*)argv + argc);
-  sim_t s(nprocs, mem_mb, htif_args);
+  sim_t s(isa, nprocs, mem_mb, htif_args);
 
   if (ic && l2) ic->set_miss_handler(&*l2);
   if (dc && l2) dc->set_miss_handler(&*l2);
@@ -76,6 +82,7 @@ int main(int argc, char** argv)
   }
 
   s.set_debug(debug);
+  s.set_log(log);
   s.set_histogram(histogram);
   return s.run();
 }