Support setting ISA/subsets with --isa flag

[riscv-isa-sim.git] / spike_main / spike.cc

diff --git a/spike_main/spike.cc b/spike_main/spike.cc
index ab5cea554957a97e388e7d71e351c94f8bffb332..7a85bd17798554dea16ff4b0447e142a923667d2 100644 (file)
--- a/spike_main/spike.cc
+++ b/spike_main/spike.cc
@@ -17,11 +17,12 @@ static void help()
 {
   fprintf(stderr, "usage: spike [host options] <target program> [target options]\n");
   fprintf(stderr, "Host Options:\n");
-  fprintf(stderr, "  -p <n>             Simulate <n> processors\n");
-  fprintf(stderr, "  -m <n>             Provide <n> MB of target memory\n");
+  fprintf(stderr, "  -p <n>             Simulate <n> processors [default 1]\n");
+  fprintf(stderr, "  -m <n>             Provide <n> MiB of target memory [default 4096]\n");
   fprintf(stderr, "  -d                 Interactive debug mode\n");
   fprintf(stderr, "  -g                 Track histogram of PCs\n");
   fprintf(stderr, "  -h                 Print this help message\n");
+  fprintf(stderr, "  --isa=<name>       RISC-V ISA string [default RV64IMAFDC]\n");
   fprintf(stderr, "  --ic=<S>:<W>:<B>   Instantiate a cache model with S sets,\n");
   fprintf(stderr, "  --dc=<S>:<W>:<B>     W ways, and B-byte blocks (with S and\n");
   fprintf(stderr, "  --l2=<S>:<W>:<B>     B both powers of 2).\n");
@@ -40,6 +41,7 @@ int main(int argc, char** argv)
   std::unique_ptr<dcache_sim_t> dc;
   std::unique_ptr<cache_sim_t> l2;
   std::function<extension_t*()> extension;
+  const char* isa = "RV64";
 
   option_parser_t parser;
   parser.help(&help);
@@ -51,6 +53,7 @@ int main(int argc, char** argv)
   parser.option(0, "ic", 1, [&](const char* s){ic.reset(new icache_sim_t(s));});
   parser.option(0, "dc", 1, [&](const char* s){dc.reset(new dcache_sim_t(s));});
   parser.option(0, "l2", 1, [&](const char* s){l2.reset(cache_sim_t::construct(s, "L2$"));});
+  parser.option(0, "isa", 1, [&](const char* s){isa = s;});
   parser.option(0, "extension", 1, [&](const char* s){extension = find_extension(s);});
   parser.option(0, "extlib", 1, [&](const char *s){
     void *lib = dlopen(s, RTLD_NOW | RTLD_GLOBAL);
@@ -64,7 +67,7 @@ int main(int argc, char** argv)
   if (!*argv1)
     help();
   std::vector<std::string> htif_args(argv1, (const char*const*)argv + argc);
-  sim_t s(nprocs, mem_mb, htif_args);
+  sim_t s(isa, nprocs, mem_mb, htif_args);
 
   if (ic && l2) ic->set_miss_handler(&*l2);
   if (dc && l2) dc->set_miss_handler(&*l2);