random modifications got semi-correct output

[ieee754fpu.git] / src / ieee754 / fpdiv / div2.py

diff --git a/src/ieee754/fpdiv/div2.py b/src/ieee754/fpdiv/div2.py
index 8fb5b8c27f0aa1e9ff4e25bf1dee4e352a7176a9..83b1e4f4aee7bf639bb292b83a00fda6812198b5 100644 (file)
--- a/src/ieee754/fpdiv/div2.py
+++ b/src/ieee754/fpdiv/div2.py
@@ -35,8 +35,6 @@ class FPDivStage2Mod(FPState, Elaboratable):
         """ links module to inputs and outputs
         """
         m.submodules.div1 = self
-        #m.submodules.div1_out_overflow = self.o.of
-
         m.d.comb += self.i.eq(i)
 
     def elaborate(self, platform):