Add separate memory clock register to SYSCON

[soc.git] / src / soc / bus / syscon.py

diff --git a/src/soc/bus/syscon.py b/src/soc/bus/syscon.py
index f8e264217c8fa9c3e96f15d28353a7fc02a0f774..f3dcfc0779ac9d1be138b9ecc3210c5b8e040e6f 100644 (file)
--- a/src/soc/bus/syscon.py
+++ b/src/soc/bus/syscon.py
@@ -2,6 +2,7 @@
 #
 # SPDX-License-Identifier: LGPLv3+
 # Copyright (C) 2022 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+# Copyright (C) 2022 Raptor Engineering, LLC <support@raptorengineering.com>
 # Sponsored by NLnet and NGI POINTER under EU Grants 871528 and 957073
 # Part of the Libre-SOC Project.
 #
@@ -21,14 +22,20 @@ class MicrowattSYSCON(Peripheral, Elaboratable):
     """
 
     def __init__(self, *, sys_clk_freq=100e6,
+                          core_clk_freq=100e6,
+                          mem_clk_freq=100e6,
                           spi_offset=None,
+                          dram_addr=None,
                           has_uart=True,
                           uart_is_16550=True
                           ):
         super().__init__(name="syscon")
         self.sys_clk_freq = sys_clk_freq
+        self.core_clk_freq = core_clk_freq
+        self.mem_clk_freq = mem_clk_freq
         self.has_uart = has_uart
         self.spi_offset = spi_offset
+        self.dram_addr = dram_addr
         self.uart_is_16550 = uart_is_16550
 
         # System control ports
@@ -45,13 +52,15 @@ class MicrowattSYSCON(Peripheral, Elaboratable):
         self._reg_info_r      = bank.csr(64, "r") # info
         self._bram_info_r     = bank.csr(64, "r") # bram info
         self._dram_info_r     = bank.csr(64, "r") # dram info
-        self._clk_info_r      = bank.csr(64, "r") # clock frequency
+        self._clk_info_r      = bank.csr(64, "r") # nest clock frequency
         self._ctrl_info_r     = bank.csr(64, "rw") # control info
         self._dram_init_r     = bank.csr(64, "r") # dram initialisation info
         self._spiflash_info_r = bank.csr(64, "r") # spi flash info
         self._uart0_info_r    = bank.csr(64, "r") # UART0 info (baud etc.)
         self._uart1_info_r    = bank.csr(64, "r") # UART1 info (baud etc.)
         self._bram_bootaddr_r = bank.csr(64, "r") # BRAM boot address
+        self._core_clk_info_r = bank.csr(64, "r") # core clock frequency
+        self._mem_clk_info_r  = bank.csr(64, "r") # memory clock frequency
 
         # bridge the above-created CSRs over wishbone.  ordering and size
         # above mattered, the bridge automatically packs them together
@@ -70,11 +79,18 @@ class MicrowattSYSCON(Peripheral, Elaboratable):
         # identifying signature
         comb += self._reg_sig_r.r_data.eq(0xf00daa5500010001)
 
-        # system clock rate (hz)
+        # nest clock rate (hz)
         comb += self._clk_info_r.r_data.eq(int(self.sys_clk_freq)) # in hz
 
+        # core clock rate (hz)
+        comb += self._core_clk_info_r.r_data.eq(int(self.core_clk_freq)) # in hz
+
+        # memory clock rate (hz)
+        comb += self._mem_clk_info_r.r_data.eq(int(self.mem_clk_freq)) # in hz
+
         # detect peripherals
         has_spi = self.spi_offset is not None
+        has_dram = self.dram_addr is not None
 
         # uart peripheral clock rate, currently assumed to be system clock
         # 0 ..31  : UART clock freq (in HZ)
@@ -84,6 +100,7 @@ class MicrowattSYSCON(Peripheral, Elaboratable):
 
         # Reg Info, defines what peripherals and characteristics are present
         comb += self._reg_info_r.r_data[0].eq(self.has_uart) # has UART0
+        comb += self._reg_info_r.r_data[1].eq(has_dram)      # has DDR DRAM
         comb += self._reg_info_r.r_data[3].eq(has_spi)       # has SPI Flash
         comb += self._reg_info_r.r_data[5].eq(1)             # Large SYSCON
 
@@ -117,7 +134,7 @@ if __name__ == "__main__":
             m = Module()
             arbiter = wishbone.Arbiter(addr_width=30, data_width=32,
                                        granularity=8)
-            decoder = wishbone.Decoder(addr_width=30, data_width=32, 
+            decoder = wishbone.Decoder(addr_width=30, data_width=32,
                                        granularity=8)
             m.submodules.syscon = syscon = MicrowattSYSCON()
             m.submodules.decoder = decoder