only add clock-settings on ECP5 due to special SPI clock handling

[soc.git] / src / soc / bus / tercel.py

diff --git a/src/soc/bus/tercel.py b/src/soc/bus/tercel.py
index 328bf661d374589f7fefc859467b55e7e9597e9f..54ba9252fb7eeeb49496531c2098101b8210955c 100644 (file)
--- a/src/soc/bus/tercel.py
+++ b/src/soc/bus/tercel.py
@@ -166,14 +166,17 @@ class Tercel(Elaboratable):
         m.submodules['tercel_%d' % self.idx] = tercel
 
         if pins is not None:
-            comb += pins.dq.o.eq(self.dq_out)
-            comb += pins.dq.oe.eq(self.dq_direction)
-            comb += pins.dq.oe.eq(self.dq_direction)
-            comb += pins.dq.o_clk.eq(ClockSignal())
-            comb += self.dq_in.eq(pins.dq.i)
-            comb += pins.dq.i_clk.eq(ClockSignal())
+            for i in range(4):
+                pad = getattr(pins, "dq%d" % i)
+                comb += pad.o.eq(self.dq_out[i])
+                comb += pad.oe.eq(self.dq_direction[i])
+                comb += self.dq_in[i].eq(pad.i)
+                # ECP5 needs special handling for the SPI clock, sigh.
+                if self.lattice_ecp5_usrmclk:
+                    comb += pad.o_clk.eq(ClockSignal())
+                    comb += pad.i_clk.eq(ClockSignal())
             # XXX invert handled by SPIFlashResource
-            comb += pins.cs.eq(~self.cs_n_out)
+            comb += pins.cs_n.eq(self.cs_n_out)
             # ECP5 needs special handling for the SPI clock, sigh.
             if self.lattice_ecp5_usrmclk:
                 m.submodules += Instance("USRMCLK",