remember to call WBAsyncBridge.add_verilog_source
"""
- def __init__(self, master_bus=None, slave_bus=None, features=None, name=None,
+ def __init__(self, master_bus=None, slave_bus=None, master_features=None,
+ slave_features=None, name=None,
address_width=30, data_width=32, granularity=8,
master_clock_domain=None, slave_clock_domain=None):
if name is not None:
self.wb_srst = ResetSignal(slave_clock_domain)
# set up the wishbone busses
- if features is None:
- features = frozenset()
+ if master_features is None:
+ master_features = frozenset()
+ if slave_features is None:
+ slave_features = frozenset()
if master_bus is None:
master_bus = Interface(addr_width=self.address_width,
data_width=self.data_width,
- features=features,
+ features=master_features,
granularity=self.granularity,
name=name+"_wb_%d_master" % self.idx)
if slave_bus is None:
slave_bus = Interface(addr_width=self.address_width,
data_width=self.data_width,
- features=features,
+ features=slave_features,
granularity=self.granularity,
name=name+"_wb_%d_slave" % self.idx)
self.master_bus = master_bus
i_wbs_rty_i=slave_rty
);
- # Synthesize STALL signal for master port
- comb += self.master_bus.stall.eq(self.master_bus.cyc & ~self.master_bus.ack)
-
- # Convert incoming slave STALL signal to a format that the async bridge understands...
- comb += slave_ack.eq(self.slave_bus.ack & ~self.slave_bus.stall)
-
# Wire unused signals to 0
comb += slave_err.eq(0)
comb += slave_rty.eq(0)
return m
def ports(self):
- return [self.master_bus.adr, self.master_bus.dat_w, self.master_bus.dat_r,
- self.master_bus.we, self.master_bus.sel, self.master_bus.stb,
- self.master_bus.cyc, self.master_bus.ack, self.master_bus.err,
+ return [self.master_bus.adr, self.master_bus.dat_w,
+ self.master_bus.dat_r,
+ self.master_bus.we, self.master_bus.sel,
+ self.master_bus.stb,
+ self.master_bus.cyc, self.master_bus.ack,
+ self.master_bus.err,
self.master_bus.rty,
- self.slave_bus.adr, self.slave_bus.dat_w, self.slave_bus.dat_r,
- self.slave_bus.we, self.slave_bus.sel, self.slave_bus.stb,
- self.slave_bus.cyc, self.slave_bus.ack, self.slave_bus.err,
+ self.slave_bus.adr, self.slave_bus.dat_w,
+ self.slave_bus.dat_r,
+ self.slave_bus.we, self.slave_bus.sel,
+ self.slave_bus.stb,
+ self.slave_bus.cyc, self.slave_bus.ack,
+ self.slave_bus.err,
self.slave_bus.rty
]
if __name__ == "__main__":
wbasyncbridge = WBAsyncBridge(name="wbasyncbridge_0", address_width=30, data_width=32, granularity=8)
- create_ilang(wbasyncbridge, wbasyncbridge.ports(), "wbasyncbridge_0")
\ No newline at end of file
+ create_ilang(wbasyncbridge, wbasyncbridge.ports(), "wbasyncbridge_0")