rename and add pll lock signal to ls180

[soc.git] / src / soc / clock / dummypll.py

diff --git a/src/soc/clock/dummypll.py b/src/soc/clock/dummypll.py
index db81eefb69ca3f050bd247731f26cb1a864e8a1f..8594f91e78638d0355919dbfa187d515aeea0862 100644 (file)
--- a/src/soc/clock/dummypll.py
+++ b/src/soc/clock/dummypll.py
@@ -10,7 +10,7 @@ class DummyPLL(Elaboratable):
         self.clk_sel_i = Signal(2, reset_less=True) # PLL selection
         self.clk_pll_o = Signal(reset_less=True)  # output fake PLL clock
         self.pll_18_o = Signal(reset_less=True)  # 16-divide from PLL
-        self.clk_lck_o = Signal(reset_less=True)  # output fake PLL "lock" 
+        self.pll_lck_o = Signal(reset_less=True)  # output fake PLL "lock"
 
     def elaborate(self, platform):
         m = Module()
@@ -18,7 +18,7 @@ class DummyPLL(Elaboratable):
         # just get something, stops yosys destroying (optimising) these out
         m.d.comb += self.pll_18_o.eq(self.clk_24_i)
         with m.If(self.clk_sel_i == Const(0, 2)):
-            m.d.comb += self.clk_lck_o.eq(self.clk_24_i)
+            m.d.comb += self.pll_lck_o.eq(self.clk_24_i)
 
         return m