rename PLL signals

[soc.git] / src / soc / clock / dummypll.py

diff --git a/src/soc/clock/dummypll.py b/src/soc/clock/dummypll.py
index fd437ef1410ba05a00581dcf10e07527e7e14491..bd87659334ae64c2cf74679109bdfe757fae52a5 100644 (file)
--- a/src/soc/clock/dummypll.py
+++ b/src/soc/clock/dummypll.py
@@ -21,7 +21,7 @@ class DummyPLL(Elaboratable):
             pll = Instance("pll", i_ref=self.clk_24_i,
                                   i_a0=self.clk_sel_i[0],
                                   i_a1=self.clk_sel_i[1],
-                                  o_out=self.clk_pll_o,
+                                  o_out_v=self.clk_pll_o,
                                   o_div_out_test=self.pll_test_o,
                                   o_vco_test_ana=self.pll_vco_o,
                            )