add DEC SPR to CoreState and PowerDecoder, activate 0x900 interrupt

[soc.git] / src / soc / config / state.py

diff --git a/src/soc/config/state.py b/src/soc/config/state.py
index e4cef69cf85dedbf6d2c9b7a3b5ea2ceecfde0d3..3fc919671fe984800d6da46c60170d19dfa8d266 100644 (file)
--- a/src/soc/config/state.py
+++ b/src/soc/config/state.py
@@ -8,3 +8,4 @@ class CoreState(RecordObject):
         self.pc = Signal(64)      # Program Counter (CIA, NIA)
         self.msr = Signal(64)     # Machine Status Register (MSR)
         self.eint = Signal()      # External Interrupt
+        self.dec = Signal(64)     # DEC SPR (again, for interrupt generation)