try making CR bitrange 32..63 not 0..31

[soc.git] / src / soc / decoder / isa / caller.py

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index deb30fc73fa57b3bf6537a36077f01316331becc..81a294d28be962b7745d67e3f590c71f5d1e2ffb 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -148,7 +148,8 @@ class ISACaller:
         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 
         # create CR then allow portions of it to be "selectable" (below)
-        self.cr = SelectableInt(0, 32) # TODO, must be bits range 32-63 not 0-31
+        self._cr = SelectableInt(0, 64) # underlying reg
+        self.cr = FieldSelectableInt(self._cr, list(range(32,64)))
 
         # "undefined", just set to variable-bit-width int (use exts "max")
         self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!