add detection of whether *full* 7-bit of RA is zero/non-zero

[soc.git] / src / soc / decoder / isa / test_caller_svp64.py

diff --git a/src/soc/decoder/isa/test_caller_svp64.py b/src/soc/decoder/isa/test_caller_svp64.py
index 1eebf7bfbd8244d764556b6328030af0cf8312a6..6441e1f5d9afe4a4ac1db9af3b382e7be6347306 100644 (file)
--- a/src/soc/decoder/isa/test_caller_svp64.py
+++ b/src/soc/decoder/isa/test_caller_svp64.py
@@ -23,21 +23,24 @@ class DecoderTestCase(FHDLTestCase):
 
     def test_sv_load_store(self):
         lst = SVP64Asm(["addi 1, 0, 0x0010",
-                        "addi 2, 0, 0x1234",
-                        "sv.stw 2, 0(1)",
-                        "sv.lwz 3, 0(1)"])
+                        "addi 2, 0, 0x0008",
+                        "addi 5, 0, 0x1234",
+                        "addi 6, 0, 0x1235",
+                        "sv.stw 5, 0(1)",
+                        "sv.lwz 9, 0(1)"])
         lst = list(lst)
 
         # SVSTATE (in this case, VL=2)
         svstate = SVP64State()
-        svstate.vl[0:7] = 1 # VL
-        svstate.maxvl[0:7] = 1 # MAXVL
+        svstate.vl[0:7] = 2 # VL
+        svstate.maxvl[0:7] = 2 # MAXVL
         print ("SVSTATE", bin(svstate.spr.asint()))
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, svstate=svstate)
             print(sim.gpr(1))
-            self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
+            self.assertEqual(sim.gpr(9), SelectableInt(0x1234, 64))
+            #self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
 
     def test_sv_add(self):
         # adds: