add syn_ramstyle "block_ram" attributes and reduce i/d-cache sizes again

[soc.git] / src / soc / experiment / dcache.py

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 0b74c4cd35fc4f084213a4f1755599c0128eb6fe..9e75cc01eb59ee42c71ffafdbcec5795c5ff12cb 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -513,12 +513,14 @@ class DTLBUpdate(Elaboratable):
         print ("    TLB_NUM_WAYS", cfg.TLB_NUM_WAYS)
 
         # TAG and PTE Memory SRAMs. transparent, write-enables are TLB_NUM_WAYS
-        tagway = Memory(depth=cfg.TLB_SET_SIZE, width=cfg.TLB_TAG_WAY_BITS)
+        tagway = Memory(depth=cfg.TLB_SET_SIZE, width=cfg.TLB_TAG_WAY_BITS,
+                             attrs={'syn_ramstyle': "block_ram"})
         m.submodules.rd_tagway = rd_tagway = tagway.read_port()
         m.submodules.wr_tagway = wr_tagway = tagway.write_port(
                                     granularity=cfg.TLB_EA_TAG_BITS)
 
-        pteway = Memory(depth=cfg.TLB_SET_SIZE, width=cfg.TLB_PTE_WAY_BITS)
+        pteway = Memory(depth=cfg.TLB_SET_SIZE, width=cfg.TLB_PTE_WAY_BITS,
+                             attrs={'syn_ramstyle': "block_ram"})
         m.submodules.rd_pteway = rd_pteway = pteway.read_port()
         m.submodules.wr_pteway = wr_pteway = pteway.write_port(
                                     granularity=cfg.TLB_PTE_BITS)
@@ -745,10 +747,10 @@ class DCache(Elaboratable, DCacheConfig):
 
         if self.microwatt_compat:
             # reduce way sizes and num lines
-            super().__init__(NUM_LINES = 16,
+            super().__init__(NUM_LINES = 4,
                               NUM_WAYS = 1,
                               TLB_NUM_WAYS = 1,
-                              TLB_SET_SIZE=16) # XXX needs device-tree entry
+                              TLB_SET_SIZE=4) # XXX needs device-tree entry
         else:
             super().__init__()
 
@@ -966,8 +968,9 @@ class DCache(Elaboratable, DCacheConfig):
 
         m_in, d_in = self.m_in, self.d_in
 
-        # synchronous tag read-port
-        m.submodules.rd_tag = rd_tag = self.tagmem.read_port()
+        # synchronous tag read-port: NOT TRANSPARENT (cannot pass through
+        # write-to-a-read at the same time), seems to pass tests ok
+        m.submodules.rd_tag = rd_tag = self.tagmem.read_port(transparent=False)
 
         index = Signal(self.INDEX_BITS)
 
@@ -1619,11 +1622,15 @@ class DCache(Elaboratable, DCacheConfig):
                     # Compare the whole address in case the
                     # request in r1.req is not the one that
                     # started this refill.
+                    rowmatch = Signal()
+                    lastrow = Signal()
+                    comb += rowmatch.eq(r1.store_row ==
+                                        self.get_row(r1.req.real_addr))
+                    comb += lastrow.eq(self.is_last_row(r1.store_row,
+                                                      r1.end_row_ix))
                     with m.If(r1.full & r1.req.same_tag &
                               ((r1.dcbz & req.dcbz) |
-                               (r1.req.op == Op.OP_LOAD_MISS)) &
-                                (r1.store_row ==
-                                 self.get_row(r1.req.real_addr))):
+                               (r1.req.op == Op.OP_LOAD_MISS)) & rowmatch):
                         sync += r1.full.eq(r1_next_cycle)
                         sync += r1.slow_valid.eq(1)
                         with m.If(r1.mmu_req):
@@ -1634,8 +1641,7 @@ class DCache(Elaboratable, DCacheConfig):
                         sync += r1.use_forward1.eq(1)
 
                     # Check for completion
-                    with m.If(ld_stbs_done & self.is_last_row(r1.store_row,
-                                                      r1.end_row_ix)):
+                    with m.If(ld_stbs_done & lastrow):
                         # Complete wishbone cycle
                         sync += r1.wb.cyc.eq(0)
 
@@ -1754,7 +1760,8 @@ class DCache(Elaboratable, DCacheConfig):
         cache_valids     = self.CacheValidsArray()
         cache_tag_set    = Signal(self.TAG_RAM_WIDTH)
 
-        self.tagmem = Memory(depth=self.NUM_LINES, width=self.TAG_RAM_WIDTH)
+        self.tagmem = Memory(depth=self.NUM_LINES, width=self.TAG_RAM_WIDTH,
+                             attrs={'syn_ramstyle': "block_ram"})
 
         """note: these are passed to nmigen.hdl.Memory as "attributes".
            don't know how, just that they are.