double the number of lines in the L1 D/I-Cache to match microwatt

[soc.git] / src / soc / experiment / icache.py

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 5417c8b365f7ea0bf3c3baf35f6c73cba9936cd7..8010bf2eab37718fd4b1c9533434dccad2d317bb 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -72,7 +72,7 @@ LINE_SIZE      = 64
 # ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
 ROW_SIZE       = WB_DATA_BITS // 8
 # Number of lines in a set
-NUM_LINES      = 16
+NUM_LINES      = 32
 # Number of ways
 NUM_WAYS       = 4
 # L1 ITLB number of entries (direct mapped)