use block_ram attribute for FPGA synthesis

[soc.git] / src / soc / experiment / icache.py

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 25a5adb4bbe93909f786decab78dcf3da4ea71a6..8e457be57a8083d30951d109cc4d47efca95edc0 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -339,6 +339,7 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
             # reduce way sizes and num lines
             ICacheConfig.__init__(self, NUM_LINES = 4,
                                         NUM_WAYS = 1,
+                                        TLB_SIZE=16 # needs device-tree update
                                  )
         else:
             ICacheConfig.__init__(self)
@@ -523,9 +524,11 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
 
         # Test if pending request is a hit on any way
         hitcond = Signal()
-        comb += hitcond.eq((r.state == State.WAIT_ACK)
-                 & (req_index == r.store_index)
-                 & r.rows_valid[req_row % self.ROW_PER_LINE]
+        rowvalid = Signal()
+        comb += rowvalid.eq(r.rows_valid[req_row % self.ROW_PER_LINE])
+        comb += hitcond.eq((r.state == State.WAIT_ACK) &
+                            (req_index == r.store_index) &
+                             rowvalid
                 )
         # i_in.req asserts Decoder active
         cvb = Signal(self.NUM_WAYS)
@@ -862,9 +865,13 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
         replace_way      = Signal(self.WAY_BITS)
 
         self.tlbmem = Memory(depth=self.TLB_SIZE,
-                             width=self.TLB_EA_TAG_BITS+self.TLB_PTE_BITS)
+                             width=self.TLB_EA_TAG_BITS+self.TLB_PTE_BITS,
+                             #attrs={'syn_ramstyle': "block_ram"}
+                            )
         self.tagmem = Memory(depth=self.NUM_LINES,
-                             width=self.TAG_RAM_WIDTH)
+                             width=self.TAG_RAM_WIDTH,
+                             #attrs={'syn_ramstyle': "block_ram"}
+                            )
 
         # call sub-functions putting everything together,
         # using shared signals established above