busy_o/1 most likely to be x_busy_o
go_die_i/1 rst?
- addr.data/48 x_addr_i (x_addr_i[:4] goes into LenExpand)
- addr.ok/1 probably x_valid_i & ~x_stall_i
+ addr.data/64 x_addr_i (x_addr_i[:4] goes into LenExpand)
+ addr.ok/1 probably x_i_valid & ~x_stall_i
addr_ok_o/1 no equivalent. *might* work using x_stall_i
- addr_exc_o/2(?) m_load_err_o and m_store_err_o
+ exc_o/6(?) m_load_err_o and m_store_err_o
ld.data/64 m_ld_data_o
ld.ok/1 probably implicit, when x_busy drops low
from nmigen import Elaboratable, Module, Signal
from nmutil.latch import SRLatch
+from nmutil.util import rising_edge
+
class Pi2LSUI(PortInterfaceBase):
def __init__(self, name, lsui=None,
- data_wid=64, mask_wid=8, addr_wid=48):
+ data_wid=64, mask_wid=8, addr_wid=64):
print("pi2lsui reg mask addr", data_wid, mask_wid, addr_wid)
super().__init__(data_wid, addr_wid)
if lsui is None:
self.lsui_busy = Signal()
self.valid_l = SRLatch(False, name="valid")
- def set_wr_addr(self, m, addr, mask):
+ def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz, is_nc):
+ print("pi2lsui TODO, implement is_dcbz")
m.d.comb += self.valid_l.s.eq(1)
m.d.comb += self.lsui.x_mask_i.eq(mask)
m.d.comb += self.lsui.x_addr_i.eq(addr)
- def set_rd_addr(self, m, addr, mask):
+ def set_rd_addr(self, m, addr, mask, misalign, msr, is_nc):
m.d.comb += self.valid_l.s.eq(1)
m.d.comb += self.lsui.x_mask_i.eq(mask)
m.d.comb += self.lsui.x_addr_i.eq(addr)
def set_wr_data(self, m, data, wen): # mask already done in addr setup
m.d.comb += self.lsui.x_st_data_i.eq(data)
- return (~self.lsui_busy)
+ return (~(self.lsui.x_busy_o | self.lsui_busy))
def get_rd_data(self, m):
return self.lsui.m_ld_data_o, ~self.lsui_busy
m.next = "WAITDEASSERT"
with m.State("WAITDEASSERT"):
# when no longer busy: back to start
- with m.If(~self.valid_l.q):
+ with m.If(~pi.is_st_i & ~pi.busy_o):
m.next = "IDLE"
- # indicate valid at both ends
- m.d.comb += self.lsui.m_valid_i.eq(self.valid_l.q)
- m.d.comb += self.lsui.x_valid_i.eq(self.valid_l.q)
+ # indicate valid at both ends. OR with lsui_busy (stops comb loop)
+ m.d.comb += self.lsui.m_i_valid.eq(self.valid_l.q )
+ m.d.comb += self.lsui.x_i_valid.eq(self.valid_l.q )
- # reset the valid latch when not busy
- m.d.comb += self.valid_l.r.eq(~self.lsui_busy)#~pi.busy_o) # self.lsui.x_busy_o)
+ # reset the valid latch when not busy. sync to stop loop
+ lsui_active = Signal()
+ m.d.comb += lsui_active.eq(~self.lsui.x_busy_o)
+ m.d.comb += self.valid_l.r.eq(rising_edge(m, lsui_active))
return m
class Pi2LSUI1(Elaboratable):
def __init__(self, name, pi=None, lsui=None,
- data_wid=64, mask_wid=8, addr_wid=48):
+ data_wid=64, mask_wid=8, addr_wid=64):
print("pi2lsui reg mask addr", data_wid, mask_wid, addr_wid)
self.addrbits = mask_wid
if pi is None:
# expand the LSBs of address plus LD/ST len into 16-bit mask
m.d.comb += lsui.x_mask_i.eq(lenexp.lexp_o)
# pass through the address, indicate "valid"
- m.d.comb += lsui.x_valid_i.eq(1)
+ m.d.comb += lsui.x_i_valid.eq(1)
# indicate "OK" - XXX should be checking address valid
m.d.comb += pi.addr_ok_o.eq(1)