forgot to pass cix (cache-inhibited) through to LD/ST which was

[soc.git] / src / soc / experiment / test / test_l0_cache_buffer2.py

diff --git a/src/soc/experiment/test/test_l0_cache_buffer2.py b/src/soc/experiment/test/test_l0_cache_buffer2.py
index 11fa645d39fc55ba7d5e91ec7531cbf08479d7da..c331a7b5e5958238a78d5c28f5fdcab873aa351d 100644 (file)
--- a/src/soc/experiment/test/test_l0_cache_buffer2.py
+++ b/src/soc/experiment/test/test_l0_cache_buffer2.py
@@ -25,10 +25,10 @@ class TestCachedMemoryPortInterface(PortInterfaceBase):
         super().__init__(regwid, addrwid)
         self.ldst = LDSTSplitter(32, 48, 4)
 
-    def set_wr_addr(self, m, addr, mask):
+    def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz, is_nc):
         m.d.comb += self.ldst.addr_i.eq(addr)
 
-    def set_rd_addr(self, m, addr, mask):
+    def set_rd_addr(self, m, addr, mask, misalign, msr, is_nc):
         m.d.comb += self.ldst.addr_i.eq(addr)
 
     def set_wr_data(self, m, data, wen):
@@ -54,7 +54,8 @@ class TestCachedMemoryPortInterface(PortInterfaceBase):
         yield from super().ports()
         # TODO: memory ports
 
-def test_cache_single_run(dut):
+
+def tst_cache_single_run(dut):
     #test single byte
     addr = 0
     data = 0xfeedface
@@ -64,7 +65,7 @@ def test_cache_single():
     dut = TestCachedMemoryPortInterface()
     #LDSTSplitter(8, 48, 4) #data leng in bytes, address bits, select bits
 
-    run_simulation(dut, test_cache_single_run(dut),
+    run_simulation(dut, tst_cache_single_run(dut),
                    vcd_name='test_cache_single.vcd')