forgot to pass cix (cache-inhibited) through to LD/ST which was

[soc.git] / src / soc / experiment / test / test_l0_cache_buffer2.py

diff --git a/src/soc/experiment/test/test_l0_cache_buffer2.py b/src/soc/experiment/test/test_l0_cache_buffer2.py
index 3a17749f80963e5cccb31ca3f5ba46256f9593e9..c331a7b5e5958238a78d5c28f5fdcab873aa351d 100644 (file)
--- a/src/soc/experiment/test/test_l0_cache_buffer2.py
+++ b/src/soc/experiment/test/test_l0_cache_buffer2.py
@@ -3,7 +3,7 @@ test cases for LDSTSplitter and L0CacheBuffer2
 """
 
 from soc.experiment.l0_cache import L0CacheBuffer2
-from nmigen import Module
+from nmigen import Module, Signal, Mux, Elaboratable, Cat, Const
 from nmigen.cli import rtlil
 from soc.scoreboard.addr_split import LDSTSplitter
 from soc.scoreboard.addr_match import LenExpand
@@ -18,29 +18,29 @@ class TestCachedMemoryPortInterface(PortInterfaceBase):
     """TestCacheMemoryPortInterface
 
     This is a test class for simple verification of LDSTSplitter
-    conforming to PortInterface,
+    conforming to PortInterface
     """
 
     def __init__(self, regwid=64, addrwid=4):
         super().__init__(regwid, addrwid)
-        #self.ldst = LDSTSplitter()
+        self.ldst = LDSTSplitter(32, 48, 4)
 
-    def set_wr_addr(self, m, addr, mask):
-        lsbaddr, msbaddr = self.splitaddr(addr)
-        #m.d.comb += self.mem.wrport.addr.eq(msbaddr)
+    def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz, is_nc):
+        m.d.comb += self.ldst.addr_i.eq(addr)
 
-    def set_rd_addr(self, m, addr, mask):
-        lsbaddr, msbaddr = self.splitaddr(addr)
-        #m.d.comb += self.mem.rdport.addr.eq(msbaddr)
+    def set_rd_addr(self, m, addr, mask, misalign, msr, is_nc):
+        m.d.comb += self.ldst.addr_i.eq(addr)
 
     def set_wr_data(self, m, data, wen):
-        #m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
-        #m.d.comb += self.mem.wrport.en.eq(wen)  # enable writes
-        return Const(1, 1) #document return value
+        m.d.comb += self.ldst.st_data_i.data.eq(data)  # write st to mem
+        m.d.comb += self.ldst.is_st_i.eq(wen)  # enable writes
+        st_ok = Const(1, 1)
+        return st_ok
 
     def get_rd_data(self, m):
-        #return self.mem.rdport.data, Const(1, 1)
-        return None 
+        # this path is still untested
+        ld_ok = Const(1, 1)
+        return self.ldst.ld_data_o.data, ld_ok
 
     def elaborate(self, platform):
         m = super().elaborate(platform)
@@ -54,7 +54,8 @@ class TestCachedMemoryPortInterface(PortInterfaceBase):
         yield from super().ports()
         # TODO: memory ports
 
-def test_cache_single_run(dut):
+
+def tst_cache_single_run(dut):
     #test single byte
     addr = 0
     data = 0xfeedface
@@ -64,7 +65,7 @@ def test_cache_single():
     dut = TestCachedMemoryPortInterface()
     #LDSTSplitter(8, 48, 4) #data leng in bytes, address bits, select bits
 
-    run_simulation(dut, test_cache_single_run(dut),
+    run_simulation(dut, tst_cache_single_run(dut),
                    vcd_name='test_cache_single.vcd')