yield
yield
+
def _test_loadstore1_ifetch_multi(dut, mem):
mmu = dut.submodules.mmu
ldst = dut.submodules.ldst
with sim.write_vcd('test_loadstore1_invalid.vcd'):
sim.run()
+
def test_loadstore1_ifetch_invalid():
m, cmpi = setup_mmu()
traces=[m.debug_status]): # include extra debug
sim.run()
+
def test_loadstore1_ifetch_multi():
m, cmpi = setup_mmu()
wbget.stop = False