set parent pspec to class with XLEN = 64

[soc.git] / src / soc / fu / div / test / test_pipe_ilang.py

diff --git a/src/soc/fu/div/test/test_pipe_ilang.py b/src/soc/fu/div/test/test_pipe_ilang.py
index ce472cad87de21c561488322a9c95d0777d61b7e..215b3a65d7e54b48e21c66bf33e36fb15b3f246a 100644 (file)
--- a/src/soc/fu/div/test/test_pipe_ilang.py
+++ b/src/soc/fu/div/test/test_pipe_ilang.py
@@ -6,7 +6,11 @@ from soc.fu.div.pipeline import DivBasePipe
 
 class TestPipeIlang(unittest.TestCase):
     def write_ilang(self, div_pipe_kind):
-        pspec = DivPipeSpec(id_wid=2, div_pipe_kind=div_pipe_kind)
+        class PPspec:
+            XLEN = 64
+        pps = PPspec()
+        pspec = DivPipeSpec(
+            id_wid=2, div_pipe_kind=div_pipe_kind, parent_pspec=pps)
         alu = DivBasePipe(pspec)
         vl = rtlil.convert(alu, ports=alu.ports())
         with open(f"div_pipeline_{div_pipe_kind.name}.il", "w") as f:
@@ -15,10 +19,10 @@ class TestPipeIlang(unittest.TestCase):
     def test_div_pipe_core(self):
         self.write_ilang(DivPipeKind.DivPipeCore)
 
-    def test_div_pipe_core(self):
+    def test_fsm_div_core(self):
         self.write_ilang(DivPipeKind.FSMDivCore)
 
-    def test_div_pipe_core(self):
+    def test_sim_only(self):
         self.write_ilang(DivPipeKind.SimOnly)