same as shiftrot, split out separate pipelines for logical

[soc.git] / src / soc / fu / logical / pipeline.py

diff --git a/src/soc/fu/logical/pipeline.py b/src/soc/fu/logical/pipeline.py
index f3c83276ee4e437b92a7f328fa23aaff45fdbd52..a0f00d1dcd6f473b77cb852d6200ccb78c982272 100644 (file)
--- a/src/soc/fu/logical/pipeline.py
+++ b/src/soc/fu/logical/pipeline.py
@@ -1,25 +1,40 @@
 from nmutil.singlepipe import ControlBase
 from nmutil.pipemodbase import PipeModBaseChain
-from soc.alu.input_stage import ALUInputStage
-from soc.logical.main_stage import LogicalMainStage
-from soc.alu.output_stage import ALUOutputStage
+from soc.fu.logical.input_stage import LogicalInputStage
+from soc.fu.logical.main_stage import LogicalMainStage
+from soc.fu.logical.output_stage import LogicalOutputStage
 
-class LogicalStages(PipeModBaseChain):
+
+class LogicalStages1(PipeModBaseChain):
+    def get_chain(self):
+        inp = LogicalInputStage(self.pspec)
+        return [inp]
+
+class LogicalStages2(PipeModBaseChain):
     def get_chain(self):
-        inp = ALUInputStage(self.pspec)
         main = LogicalMainStage(self.pspec)
-        out = ALUOutputStage(self.pspec)
-        return [inp, main, out]
+        return [main]
+
+
+class LogicalStages3(PipeModBaseChain):
+    def get_chain(self):
+        out = LogicalOutputStage(self.pspec)
+        return [out]
 
 
 class LogicalBasePipe(ControlBase):
     def __init__(self, pspec):
         ControlBase.__init__(self)
-        self.pipe1 = LogicalStages(pspec)
-        self._eqs = self.connect([self.pipe1])
+        self.pspec = pspec
+        self.pipe1 = LogicalStages1(pspec)
+        self.pipe2 = LogicalStages2(pspec)
+        self.pipe3 = LogicalStages3(pspec)
+        self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3])
 
     def elaborate(self, platform):
         m = ControlBase.elaborate(self, platform)
-        m.submodules.pipe = self.pipe1
+        m.submodules.logical_pipe1 = self.pipe1
+        m.submodules.logical_pipe2 = self.pipe2
+        m.submodules.logical_pipe3 = self.pipe3
         m.d.comb += self._eqs
         return m