set parent pspec to class with XLEN = 64

[soc.git] / src / soc / fu / mul / test / helper.py

diff --git a/src/soc/fu/mul/test/helper.py b/src/soc/fu/mul/test/helper.py
index b32e2dc6359cb96a934b4d10382f4d1012389a4b..30cb94966d3292916d94b7e809ad70f88e55e609 100644 (file)
--- a/src/soc/fu/mul/test/helper.py
+++ b/src/soc/fu/mul/test/helper.py
@@ -8,31 +8,30 @@ import power_instruction_analyzer as pia
 
 from nmigen.cli import rtlil
 import unittest
-from soc.decoder.isa.caller import ISACaller, special_sprs
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
-from soc.decoder.selectable_int import SelectableInt
-from soc.simulator.program import Program
-from soc.decoder.isa.all import ISA
-from soc.config.endian import bigendian
-
-from soc.fu.test.common import (TestAccumulatorBase, TestCase, ALUHelpers)
+from openpower.decoder.isa.caller import ISACaller, special_sprs
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.simulator.program import Program
+from openpower.decoder.isa.all import ISA
+from openpower.endian import bigendian
+
+from openpower.test.common import (TestAccumulatorBase, TestCase, ALUHelpers)
 from soc.fu.test.pia import pia_res_to_output
 from soc.fu.mul.pipeline import MulBasePipe
 from soc.fu.mul.pipe_data import MulPipeSpec
 import random
 
 
-def get_cu_inputs(dec2, sim, has_third_input):
+def get_cu_inputs(dec2, sim):
     """naming (res) must conform to MulFunctionUnit input regspec
     """
     res = {}
 
     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2)  # RA
     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2)  # RB
-    if has_third_input:
-        yield from ALUHelpers.get_sim_int_rc(res, sim, dec2)  # RC
+    yield from ALUHelpers.get_sim_int_rc(res, sim, dec2)  # RC
     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2)  # XER.so
 
     print("alu get_cu_inputs", res)
@@ -43,9 +42,9 @@ def get_cu_inputs(dec2, sim, has_third_input):
 def set_alu_inputs(alu, dec2, sim, has_third_input):
     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
-    # and place it into data_i.b
+    # and place it into i_data.b
 
-    inp = yield from get_cu_inputs(dec2, sim, has_third_input)
+    inp = yield from get_cu_inputs(dec2, sim)
     print("set alu inputs", inp)
     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
@@ -60,8 +59,14 @@ def set_alu_inputs(alu, dec2, sim, has_third_input):
         overflow = pia.OverflowFlags(so=bool(so),
                                      ov=False,
                                      ov32=False)
-    rc = inp["rb"] if has_third_input else None
-    return pia.InstructionInput(ra=inp["ra"], rb=inp["rb"],
+    immediate_ok = yield dec2.e.do.imm_data.ok
+    if immediate_ok:
+        immediate = yield dec2.e.do.imm_data.data
+    else:
+        immediate = None
+    rc = inp["rc"] if has_third_input else None
+    return pia.InstructionInput(ra=inp.get("ra"), rb=inp.get("rb"),
+                                immediate=immediate,
                                 rc=rc, overflow=overflow)
 
 
@@ -97,25 +102,25 @@ class MulTestHelper(unittest.TestCase):
                                                    has_third_input)
 
             # set valid for one cycle, propagate through pipeline...
-            yield alu.p.valid_i.eq(1)
+            yield alu.p.i_valid.eq(1)
             yield
-            yield alu.p.valid_i.eq(0)
+            yield alu.p.i_valid.eq(0)
 
             opname = code.split(' ')[0]
             fnname = opname.replace(".", "_")
             print(f"{fnname}({pia_inputs})")
-            pia_res = getattr(pia, opname.replace(".", "_"))(pia_inputs)
+            pia_res = getattr(pia, fnname)(pia_inputs)
             print(f"-> {pia_res}")
 
             yield from isa_sim.call(opname)
             index = isa_sim.pc.CIA.value//4
 
             # ...wait for valid to pop out the end
-            vld = yield alu.n.valid_o
+            vld = yield alu.n.o_valid
             while not vld:
                 yield
                 yield Delay(0.1e-6)
-                vld = yield alu.n.valid_o
+                vld = yield alu.n.o_valid
             yield Delay(0.1e-6)
 
             # XXX sim._engine is an internal variable
@@ -141,11 +146,14 @@ class MulTestHelper(unittest.TestCase):
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
         pdecode = pdecode2.dec
 
-        pspec = MulPipeSpec(id_wid=2)
+        class PPspec:
+            XLEN = 64
+        pps = PPspec()
+        pspec = MulPipeSpec(id_wid=2, parent_pspec=pps)
         m.submodules.alu = alu = MulBasePipe(pspec)
 
-        comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
-        comb += alu.n.ready_i.eq(1)
+        comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
+        comb += alu.n.i_ready.eq(1)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
         sim = Simulator(m)
 
@@ -176,8 +184,8 @@ class MulTestHelper(unittest.TestCase):
         oe_ok = yield dec2.e.do.oe.ok
         if not oe or not oe_ok:
             # if OE not enabled, XER SO and OV must correspondingly be false
-            so_ok = yield alu.n.data_o.xer_so.ok
-            ov_ok = yield alu.n.data_o.xer_ov.ok
+            so_ok = yield alu.n.o_data.xer_so.ok
+            ov_ok = yield alu.n.o_data.xer_ov.ok
             self.assertEqual(so_ok, False, code)
             self.assertEqual(ov_ok, False, code)