add 3 more 4k SRAMs, change WB bus width to 64 in ls180 litex

[soc.git] / src / soc / litex / florent / Makefile

diff --git a/src/soc/litex/florent/Makefile b/src/soc/litex/florent/Makefile
index 754d5d083956ec4b9df405784b30d0c6ee511972..d1c5cc1de0ba7de83fb19a827cc20202bb3fdbf0 100644 (file)
--- a/src/soc/litex/florent/Makefile
+++ b/src/soc/litex/florent/Makefile
@@ -2,6 +2,9 @@ ls180:
        ./ls180soc.py --build --platform=ls180
        cp build/ls180/gateware/ls180.v .
        cp build/ls180/gateware/mem.init .
+       cp build/ls180/gateware/mem_1.init .
+       cp build/ls180/gateware/mem_2.init .
+       cp build/ls180/gateware/mem_3.init .
        cp libresoc/libresoc.v .
        yosys -p 'read_verilog libresoc.v' \
           -p 'write_ilang libresoc_cvt.il'