if variant == "ls180":
self.pll_18_o = Signal()
self.clk_sel = Signal(3)
+ self.pll_lck_o = Signal()
self.cpu_params['i_clk_sel_i'] = self.clk_sel
self.cpu_params['o_pll_18_o'] = self.pll_18_o
+ self.cpu_params['o_pll_lck_o'] = self.pll_lck_o
# add wishbone buses to cpu params
self.cpu_params.update(make_wb_bus("ibus", ibus))