add litex wishbone interconnect to 4x 4k SRAMs

[soc.git] / src / soc / litex / florent / libresoc / core.py

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 12112b6610be8a917b3a8425e42b960bfd37244d..189216e241b0ec5fbd51a3bce826edc376f11c5e 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -29,19 +29,23 @@ def make_wb_bus(prefix, obj, simple=False):
         res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
     return res
 
-def make_wb_slave(prefix, obj):
+def make_wb_slave(prefix, obj, simple=False):
     res = {}
-    for i in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']:
+    inpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
+    if not simple:
+        inpins += ['cti', 'bte']
+    for i in inpins:
         res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
     for o in ['ack', 'err', 'dat_r']:
         res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
     return res
 
 def make_pad(res, dirn, name, suffix, cpup, iop):
-    print ("make pad", dirn, name, suffix, cpup, iop)
     cpud, iod = ('i', 'o') if dirn else ('o', 'i')
-    res['%s_%s__core__%s' % (cpud, name, suffix)] = cpup
-    res['%s_%s__pad__%s' % (iod, name, suffix)] = iop
+    cname = '%s_%s__core__%s' % (cpud, name, suffix)
+    pname = '%s_%s__pad__%s' % (iod, name, suffix)
+    print ("make pad", name, dirn, cpud, iod, cname, pname, suffix, cpup, iop)
+    res[cname], res[pname] = cpup, iop
 
 def get_field(rec, name):
     for f in rec.layout:
@@ -77,10 +81,12 @@ def make_jtag_ioconn(res, pin, cpupads, iopads):
         elif len(ps) == 2 and ps[-1].isdigit():
             pin, idx = ps
             idx = int(idx)
+            print ("ps split", pin, idx)
             cpup = getattr(cpu, pin)[idx]
             iop = getattr(io, pin)[idx]
         elif pin.isdigit():
             idx = int(pin)
+            print ("digit", idx)
             cpup = cpu[idx]
             iop = io[idx]
         else:
@@ -95,7 +101,7 @@ def make_jtag_ioconn(res, pin, cpupads, iopads):
     elif iotype == IOType.In:
         # input to the pad is routed through C4M JTAG and so
         # is an *OUTPUT* into core.  ls180soc connects this to "real" peripheral
-        make_pad(res, False, name, "i", cpup, iop)
+        make_pad(res, True, name, "i", cpup, iop)
 
     elif iotype == IOType.InTriOut:
         if fn == 'gpio': # sigh decode GPIO special-case
@@ -109,7 +115,7 @@ def make_jtag_ioconn(res, pin, cpupads, iopads):
             oe_idx = 0
         print ("gpio tri", fn, pin, iotype, pin_name, scan_idx, idx)
         cpup, iop = get_field(cpu, "i")[idx], get_field(io, "i")[idx]
-        make_pad(res, False, name, "i", cpup, iop)
+        make_pad(res, True, name, "i", cpup, iop)
         cpup, iop = get_field(cpu, "o")[idx], get_field(io, "o")[idx]
         make_pad(res, True, name, "o", cpup, iop)
         cpup, iop = get_field(cpu, "oe")[oe_idx], get_field(io, "oe")[oe_idx]
@@ -181,6 +187,11 @@ class LibreSoC(CPU):
         if jtag_en:
             self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
 
+        if "sram4k" in variant or variant == 'ls180':
+            self.srams = srams = []
+            for i in range(4):
+                srams.append(wb.Interface(data_width=64, adr_width=29))
+
         self.periph_buses = [ibus, dbus]
         self.memory_buses = []
 
@@ -240,21 +251,30 @@ class LibreSoC(CPU):
         # add clock select, pll output
         if variant == "ls180":
             self.pll_18_o = Signal()
-            self.clk_sel = Signal(3)
+            self.clk_sel = Signal(2)
             self.pll_lck_o = Signal()
             self.cpu_params['i_clk_sel_i'] = self.clk_sel
             self.cpu_params['o_pll_18_o'] = self.pll_18_o
             self.cpu_params['o_pll_lck_o'] = self.pll_lck_o
 
         # add wishbone buses to cpu params
-        self.cpu_params.update(make_wb_bus("ibus", ibus))
-        self.cpu_params.update(make_wb_bus("dbus", dbus))
-        self.cpu_params.update(make_wb_slave("ics_wb", ics))
-        self.cpu_params.update(make_wb_slave("icp_wb", icp))
+        self.cpu_params.update(make_wb_bus("ibus", ibus, True))
+        self.cpu_params.update(make_wb_bus("dbus", dbus, True))
+        self.cpu_params.update(make_wb_slave("ics_wb", ics, True))
+        self.cpu_params.update(make_wb_slave("icp_wb", icp, True))
         if "testgpio" in variant:
             self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
         if jtag_en:
             self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
+        if "sram4k" in variant or variant == 'ls180':
+            for i, sram in enumerate(srams):
+                self.cpu_params.update(make_wb_slave("sram4k_%d_wb" % i, sram))
+
+        # and set ibus advanced tags to zero (disable)
+        self.cpu_params['i_ibus__cti'] = 0
+        self.cpu_params['i_ibus__bte'] = 0
+        self.cpu_params['i_dbus__cti'] = 0
+        self.cpu_params['i_dbus__bte'] = 0
 
         if variant == 'ls180':
             # urr yuk.  have to expose iopads / pins from core to litex