from litex.build.generic_platform import ConstraintManager
-CPU_VARIANTS = ["standard", "standard32", "standardjtag", "ls180"]
+CPU_VARIANTS = ["standard", "standard32", "standardjtag",
+ "standardjtagtestgpio", "ls180",
+ "standardjtagnoirq"]
def make_wb_bus(prefix, obj, simple=False):
res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
return res
-def make_wb_slave(prefix, obj):
+def make_wb_slave(prefix, obj, simple=False):
res = {}
- for i in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']:
+ inpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
+ if not simple:
+ inpins += ['cti', 'bte']
+ for i in inpins:
res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
for o in ['ack', 'err', 'dat_r']:
res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
def make_pad(res, dirn, name, suffix, cpup, iop):
cpud, iod = ('i', 'o') if dirn else ('o', 'i')
- res['%s_%s__core__%s' % (cpud, name, suffix)] = cpup
- res['%s_%s__pad__%s' % (iod, name, suffix)] = iop
+ cname = '%s_%s__core__%s' % (cpud, name, suffix)
+ pname = '%s_%s__pad__%s' % (iod, name, suffix)
+ print ("make pad", name, dirn, cpud, iod, cname, pname, suffix, cpup, iop)
+ res[cname], res[pname] = cpup, iop
def get_field(rec, name):
for f in rec.layout:
elif len(ps) == 2 and ps[-1].isdigit():
pin, idx = ps
idx = int(idx)
+ print ("ps split", pin, idx)
cpup = getattr(cpu, pin)[idx]
iop = getattr(io, pin)[idx]
elif pin.isdigit():
idx = int(pin)
+ print ("digit", idx)
cpup = cpu[idx]
iop = io[idx]
else:
elif iotype == IOType.In:
# input to the pad is routed through C4M JTAG and so
# is an *OUTPUT* into core. ls180soc connects this to "real" peripheral
- make_pad(res, False, name, "i", cpup, iop)
+ make_pad(res, True, name, "i", cpup, iop)
elif iotype == IOType.InTriOut:
if fn == 'gpio': # sigh decode GPIO special-case
idx = int(pin[1:])
+ oe_idx = idx
+ elif fn == 'sdr': # sigh
+ idx = int(pin.split('_')[-1])
+ oe_idx = 0
else:
idx = 0
+ oe_idx = 0
+ print ("gpio tri", fn, pin, iotype, pin_name, scan_idx, idx)
cpup, iop = get_field(cpu, "i")[idx], get_field(io, "i")[idx]
- make_pad(res, False, name, "i", cpup, iop)
+ make_pad(res, True, name, "i", cpup, iop)
cpup, iop = get_field(cpu, "o")[idx], get_field(io, "o")[idx]
make_pad(res, True, name, "o", cpup, iop)
- cpup, iop = get_field(cpu, "oe")[idx], get_field(io, "oe")[idx]
+ cpup, iop = get_field(cpu, "oe")[oe_idx], get_field(io, "oe")[oe_idx]
make_pad(res, True, name, "oe", cpup, iop)
if iotype in (IOType.In, IOType.InTriOut):
self.platform = platform
self.variant = variant
self.reset = Signal()
+
irq_en = "noirq" not in variant
if irq_en:
jtag_en = ('jtag' in variant) or variant == 'ls180'
- if variant != "ls180":
+ if "testgpio" in variant:
self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
if jtag_en:
self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
+ if "sram4k" in variant or variant == 'ls180':
+ self.srams = srams = []
+ for i in range(4):
+ srams.append(wb.Interface(data_width=64, adr_width=29))
+
self.periph_buses = [ibus, dbus]
self.memory_buses = []
o_busy_o = Signal(), # not connected
o_memerr_o = Signal(), # not connected
o_pc_o = Signal(64), # not connected
-
)
if irq_en:
# add clock select, pll output
if variant == "ls180":
- self.pll_48_o = Signal()
- self.clk_sel = Signal(3)
+ self.pll_18_o = Signal()
+ self.clk_sel = Signal(2)
+ self.pll_lck_o = Signal()
self.cpu_params['i_clk_sel_i'] = self.clk_sel
- self.cpu_params['o_pll_48_o'] = self.pll_48_o
-
+ self.cpu_params['o_pll_18_o'] = self.pll_18_o
+ self.cpu_params['o_pll_lck_o'] = self.pll_lck_o
+
# add wishbone buses to cpu params
- self.cpu_params.update(make_wb_bus("ibus", ibus))
- self.cpu_params.update(make_wb_bus("dbus", dbus))
- self.cpu_params.update(make_wb_slave("ics_wb", ics))
- self.cpu_params.update(make_wb_slave("icp_wb", icp))
- if variant != "ls180":
+ self.cpu_params.update(make_wb_bus("ibus", ibus, True))
+ self.cpu_params.update(make_wb_bus("dbus", dbus, True))
+ self.cpu_params.update(make_wb_slave("ics_wb", ics, True))
+ self.cpu_params.update(make_wb_slave("icp_wb", icp, True))
+ if "testgpio" in variant:
self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
if jtag_en:
self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
+ if "sram4k" in variant or variant == 'ls180':
+ for i, sram in enumerate(srams):
+ self.cpu_params.update(make_wb_slave("sram4k_%d_wb" % i, sram))
+
+ # and set ibus advanced tags to zero (disable)
+ self.cpu_params['i_ibus__cti'] = 0
+ self.cpu_params['i_ibus__bte'] = 0
+ self.cpu_params['i_dbus__cti'] = 0
+ self.cpu_params['i_dbus__bte'] = 0
if variant == 'ls180':
# urr yuk. have to expose iopads / pins from core to litex