class GPIOTristateASIC(Module, AutoCSR):
- def __init__(self, pads):
+ def __init__(self, pads, prange=None):
nbits = len(pads.oe) # hack
self._oe = CSRStorage(nbits, description="GPIO Tristate(s) Control.")
self._in = CSRStatus(nbits, description="GPIO Input(s) Status.")
self.comb += _pads.oe.eq(self._oe.storage)
self.comb += _pads.o.eq(self._out.storage)
- for i in range(nbits):
+ if prange is None:
+ prange = range(nbits)
+ for i in prange:
self.specials += MultiReg(_pads.i[i], self._in.status[i])
# SDCard PHY IO -------------------------------------------------------
self.mem_map["main_ram"] = 0x90000000
self.mem_map["sram"] = 0x00000000
+ self.mem_map["sram1"] = 0x00000200
+ self.mem_map["sram2"] = 0x00000400
+ self.mem_map["sram3"] = 0x00000600
+ self.mem_map["sram4"] = 0x00000800
+ self.mem_map["sram4k_0"] = 0x00001000
+ self.mem_map["sram4k_1"] = 0x00002000
+ self.mem_map["sram4k_2"] = 0x00003000
+ self.mem_map["sram4k_3"] = 0x00004000
# SoCCore -------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
cpu_type = "microwatt",
cpu_cls = LibreSoC if cpu == "libresoc" \
else Microwatt,
- #bus_data_width = 64,
+ bus_data_width = 64,
csr_address_width = 14, # limit to 0x8000
cpu_variant = variant,
csr_data_width = 8,
sdram_module = sdram_module,
sdram_data_width = sdram_data_width,
integrated_rom_size = 0, # if ram_fname else 0x10000,
+ #integrated_sram_size = 0x1000, - problem with yosys ABC
integrated_sram_size = 0x200,
#integrated_main_ram_init = ram_init,
integrated_main_ram_size = 0x00000000 if with_sdram \
)
self.platform.name = "ls180"
+ # add 4 more 4k integrated SRAMs
+ self.add_ram("sram1", self.mem_map["sram1"], 0x200)
+ self.add_ram("sram2", self.mem_map["sram2"], 0x200)
+ self.add_ram("sram3", self.mem_map["sram3"], 0x200)
+ self.add_ram("sram4", self.mem_map["sram4"], 0x200)
+
# SDR SDRAM ----------------------------------------------
if False: # not self.integrated_main_ram_size:
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
ics_region = SoCRegion(origin=ics_addr, size=0x1000, cached=False)
self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
+ # add 4x 4k SRAMs
+ for i, sram_wb in enumerate(self.cpu.srams):
+ name = 'sram4k_%d' % i
+ sram_adr = self.mem_map[name]
+ ics_region = SoCRegion(origin=sram_adr, size=0x1000)
+ self.bus.add_slave(name=name, slave=sram_wb, region=ics_region)
+
# CRG -----------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"),
platform.request("sys_rst"))
# GPIOs (bi-directional)
gpio_core_pads = self.cpu.cpupads['gpio']
- self.submodules.gpio = GPIOTristateASIC(gpio_core_pads)
+ self.submodules.gpio = GPIOTristateASIC(gpio_core_pads, range(8))
self.add_csr("gpio")
+ self.submodules.gpio = GPIOTristateASIC(gpio_core_pads, range(8,16))
+ self.add_csr("gpio1")
+
# SPI Master
print ("cpupadkeys", self.cpu.cpupads.keys())
self.submodules.spimaster = SPIMaster(