from libresoc import LibreSoC
from microwatt import Microwatt
+# HACK!
+from litex.soc.integration.soc import SoCCSRHandler
+SoCCSRHandler.supported_address_width.append(12)
+
# LibreSoCSim -----------------------------------------------------------------
class LibreSoCSim(SoCSDRAM):
- def __init__(self, cpu="libresoc", debug=False, with_sdram=True,
+ def __init__(self, cpu="libresoc", variant="standardjtag", debug=False,
+ with_sdram=True,
sdram_module = "AS4C16M16",
#sdram_data_width = 16,
#sdram_module = "MT48LC16M16",
sdram_data_width = 16,
+ irq_reserved_irqs = {'uart': 0},
):
assert cpu in ["libresoc", "microwatt"]
platform = Platform()
sys_clk_freq = int(100e6)
- #cpu_data_width = 32
- cpu_data_width = 64
-
- if cpu_data_width == 32:
- variant = "standard32"
- else:
- variant = "standard"
-
#ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
# "hello_world/hello_world.bin"
- ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
- "tests/1.bin"
+ #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+ # "tests/1.bin"
#ram_fname = "/tmp/test.bin"
- #ram_fname = None
+ #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+ # "micropython/firmware.bin"
+ #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+ # "tests/xics/xics.bin"
+ #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+ # "tests/decrementer/decrementer.bin"
+ #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+ # "hello_world/hello_world.bin"
+ ram_fname = None
+
+ # reserve XICS ICP and XICS memory addresses.
+ self.mem_map['icp'] = 0xc0004000
+ self.mem_map['ics'] = 0xc0005000
+ self.mem_map['gpio'] = 0xc0007000
+ #self.csr_map["icp"] = 8 # 8 x 0x800 == 0x4000
+ #self.csr_map["ics"] = 10 # 10 x 0x800 == 0x5000
ram_init = []
if ram_fname:
# without sram nothing works, therefore move it to higher up
self.mem_map["sram"] = 0x90000000
+ # put UART at 0xc000200 (w00t! this works!)
+ self.csr_map["uart"] = 4
+
# SoCCore -------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
cpu_cls = LibreSoC if cpu == "libresoc" \
else Microwatt,
#bus_data_width = 64,
+ csr_address_width = 12, # limit to 0x4000
cpu_variant = variant,
- csr_data_width = 32,
+ csr_data_width = 8,
l2_size = 0,
uart_name = "sim",
with_sdram = with_sdram,
)
self.platform.name = "sim"
+ if cpu == "libresoc":
+ # XICS interrupt devices
+ icp_addr = self.mem_map['icp']
+ icp_wb = self.cpu.xics_icp
+ icp_region = SoCRegion(origin=icp_addr, size=0x20, cached=False)
+ self.bus.add_slave(name='icp', slave=icp_wb, region=icp_region)
+
+ ics_addr = self.mem_map['ics']
+ ics_wb = self.cpu.xics_ics
+ ics_region = SoCRegion(origin=ics_addr, size=0x1000, cached=False)
+ self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
+
+ if "gpio" in variant:
+ # Simple GPIO peripheral
+ gpio_addr = self.mem_map['gpio']
+ gpio_wb = self.cpu.simple_gpio
+ gpio_region = SoCRegion(origin=gpio_addr, size=0x20, cached=False)
+ self.bus.add_slave(name='gpio', slave=gpio_wb, region=gpio_region)
+
+
# CRG -----------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"))
self.add_constant("MEMTEST_DATA_DEBUG", 1)
+ # add JTAG platform pins
+ platform.add_extension([
+ ("jtag", 0,
+ Subsignal("tck", Pins(1)),
+ Subsignal("tms", Pins(1)),
+ Subsignal("tdi", Pins(1)),
+ Subsignal("tdo", Pins(1)),
+ )
+ ])
+
+ jtagpads = platform.request("jtag")
+ self.comb += self.cpu.jtag_tck.eq(jtagpads.tck)
+ self.comb += self.cpu.jtag_tms.eq(jtagpads.tms)
+ self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi)
+ self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo)
+
+
# Debug ---------------------------------------------------------------
if not debug:
return
pc = Signal(64)
active_dbg = Signal()
active_dbg_cr = Signal()
+ active_dbg_xer = Signal()
+
+ # xer flags
+ xer_so = Signal()
+ xer_ca = Signal()
+ xer_ca32 = Signal()
+ xer_ov = Signal()
+ xer_ov32 = Signal()
# increment counter, Stop after 100000 cycles
uptime = Signal(64)
)
)
+ self.comb += xer_so.eq((dbg_dout & 1) == 1)
+ self.comb += xer_ca.eq((dbg_dout & 4) == 4)
+ self.comb += xer_ca32.eq((dbg_dout & 8) == 8)
+ self.comb += xer_ov.eq((dbg_dout & 16) == 16)
+ self.comb += xer_ov32.eq((dbg_dout & 32) == 32)
+
# debug messages out
self.sync += If(dbg_msg,
(If(active_dbg & (dbg_addr == 0b10), # PC
# Display(" msr: %016x", dbg_dout),
#),
If(dbg_addr == 0b1000, # CR
- Display(" cr: %016x", dbg_dout),
+ Display(" cr : %016x", dbg_dout),
+ ),
+ If(dbg_addr == 0b1001, # XER
+ Display(" xer: so %d ca %d 32 %d ov %d 32 %d",
+ xer_so, xer_ca, xer_ca32, xer_ov, xer_ov32),
),
If(dbg_addr == 0b101, # GPR
Display(" gpr: %016x", dbg_dout),
)
if cpu == "libresoc":
- self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x1094c))
- #self.comb += active_dbg_cr.eq(1)
+ #self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x12600))
+ self.comb += active_dbg_cr.eq(0)
# get the CR
self.sync += If(active_dbg_cr & (dmicount == 16),
)
)
+ #self.comb += active_dbg_xer.eq((0x10300 <= pc) & (pc <= 0x1094c))
+ self.comb += active_dbg_xer.eq(active_dbg_cr)
+
+ # get the CR
+ self.sync += If(active_dbg_xer & (dmicount == 20),
+ (dmi_addr.eq(0b1001), # XER
+ dmi_req.eq(1),
+ dmi_wen.eq(0),
+ )
+ )
+
# read all 32 GPRs
for i in range(32):
- self.sync += If(active_dbg & (dmicount == 20+(i*8)),
+ self.sync += If(active_dbg & (dmicount == 24+(i*8)),
(dmi_addr.eq(0b100), # GSPR addr
dmi_din.eq(i), # r1
dmi_req.eq(1),
)
)
- self.sync += If(active_dbg & (dmicount == 24+(i*8)),
+ self.sync += If(active_dbg & (dmicount == 28+(i*8)),
(dmi_addr.eq(0b101), # GSPR data
dmi_req.eq(1),
dmi_wen.eq(0),
parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Sim")
parser.add_argument("--cpu", default="libresoc",
help="CPU to use: libresoc (default) or microwatt")
+ parser.add_argument("--variant", default="standardjtag",
+ help="Specify variant with different features")
parser.add_argument("--debug", action="store_true",
help="Enable debug traces")
parser.add_argument("--trace", action="store_true",
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
+ sim_config.add_module("jtagremote", "jtag", args={'port': 44853})
for i in range(2):
- soc = LibreSoCSim(cpu=args.cpu, debug=args.debug)
+ soc = LibreSoCSim(cpu=args.cpu, debug=args.debug, variant=args.variant)
builder = Builder(soc,compile_gateware = i!=0)
builder.build(sim_config=sim_config,
run = i!=0,
projects / soc.git / blobdiff