versa_ecp5 adds ability to build and load for ulx3s85f, fixes testgpio

feature

diff --git a/Makefile b/Makefile
index 4f3abd1cb71cc0055abd7bf0af841e3da6ed8b01..9d7ae554eb38300625e81f7360b4a75107120e2f 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -18,9 +18,15 @@ develop:
        python3 src/soc/decoder/pseudo/pywriter.py
 
 run_sim: install
-       python3 src/soc/simple/issuer_verilog.py src/soc/litex/florent/libresoc/libresoc.v
+       python3 src/soc/simple/issuer_verilog.py src/soc/litex/florent/\
+       libresoc/libresoc.v
        python3 src/soc/litex/florent/sim.py --cpu=libresoc
 
+testgpio_run_sim:
+       python3 src/soc/simple/issuer_verilog.py src/soc/litex/florent/libresoc/\
+       libresoc.v --enable-testgpio
+       python3 src/soc/litex/florent/sim.py --cpu=libresoc --variant=standardjtagtestgpio
+
 test: install
        python3 setup.py test # could just run nosetest3...
 

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 81bd0dfc400087e6fc09f3fbf1c42d380d93550c..d56a524994019f15666762073cae70c60b2a556f 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -13,7 +13,8 @@ from libresoc.ls180 import io
 from litex.build.generic_platform import ConstraintManager
 
 
-CPU_VARIANTS = ["standard", "standard32", "standardjtag", "ls180",
+CPU_VARIANTS = ["standard", "standard32", "standardjtag",
+                "standardjtagtestgpio", "ls180",
                 "standardjtagnoirq"]
 
 
@@ -167,7 +168,7 @@ class LibreSoC(CPU):
 
         jtag_en = ('jtag' in variant) or variant == 'ls180'
 
-        if "gpiotest" in variant:
+        if "testgpio" in variant:
             self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
         if jtag_en:
             self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
@@ -235,13 +236,13 @@ class LibreSoC(CPU):
             self.clk_sel = Signal(3)
             self.cpu_params['i_clk_sel_i'] = self.clk_sel
             self.cpu_params['o_pll_48_o'] = self.pll_48_o
-    
+
         # add wishbone buses to cpu params
         self.cpu_params.update(make_wb_bus("ibus", ibus))
         self.cpu_params.update(make_wb_bus("dbus", dbus))
         self.cpu_params.update(make_wb_slave("ics_wb", ics))
         self.cpu_params.update(make_wb_slave("icp_wb", icp))
-        if "gpiotest" in variant:
+        if "testgpio" in variant:
             self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
         if jtag_en:
             self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index c797a43d8ba56d698e624ac7a0dc152f31226fe6..d3687aa4515fa6ecaee22d406e59e50ac0f3bfba 100755 (executable)
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -32,7 +32,8 @@ SoCCSRHandler.supported_address_width.append(12)
 # LibreSoCSim -----------------------------------------------------------------
 
 class LibreSoCSim(SoCSDRAM):
-    def __init__(self, cpu="libresoc", debug=False, with_sdram=True,
+    def __init__(self, cpu="libresoc", variant="standardjtag", debug=False,
+            with_sdram=True,
             sdram_module          = "AS4C16M16",
             #sdram_data_width      = 16,
             #sdram_module          = "MT48LC16M16",
@@ -43,14 +44,6 @@ class LibreSoCSim(SoCSDRAM):
         platform     = Platform()
         sys_clk_freq = int(100e6)
 
-        #cpu_data_width = 32
-        cpu_data_width = 64
-
-        if cpu_data_width == 32:
-            variant = "standard32"
-        else:
-            variant = "standardjtag"
-
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "hello_world/hello_world.bin"
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
@@ -124,6 +117,7 @@ class LibreSoCSim(SoCSDRAM):
             ics_region = SoCRegion(origin=ics_addr, size=0x1000, cached=False)
             self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
 
+        if "gpio" in variant:
             # Simple GPIO peripheral
             gpio_addr = self.mem_map['gpio']
             gpio_wb = self.cpu.simple_gpio
@@ -451,6 +445,8 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Sim")
     parser.add_argument("--cpu",          default="libresoc",
                         help="CPU to use: libresoc (default) or microwatt")
+    parser.add_argument("--variant",      default="standardjtag",
+                        help="Specify variant with different features")
     parser.add_argument("--debug",        action="store_true",
                         help="Enable debug traces")
     parser.add_argument("--trace",        action="store_true",
@@ -466,7 +462,7 @@ def main():
     sim_config.add_module("jtagremote", "jtag", args={'port': 44853})
 
     for i in range(2):
-        soc = LibreSoCSim(cpu=args.cpu, debug=args.debug)
+        soc = LibreSoCSim(cpu=args.cpu, debug=args.debug, variant=args.variant)
         builder = Builder(soc,compile_gateware = i!=0)
         builder.build(sim_config=sim_config,
             run         = i!=0,

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 92ec2f54a25815ec82e7c7948c6a47a1d785610b..c9483be22857c6c983933c1d4f9c1c52b27b1aae 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -38,6 +38,7 @@ if __name__ == '__main__':
              'mul': 1,
              'shiftrot': 1
             }
+
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
                          imem_ifacetype='bare_wb',
                          addr_wid=48,
@@ -55,6 +56,12 @@ if __name__ == '__main__':
                          debug=args.debug,      # set to jtag or dmi
                          units=units)
 
+    print("nocore", pspec.__dict__["nocore"])
+    print("gpio", pspec.__dict__["gpio"])
+    print("xics", pspec.__dict__["xics"])
+    print("use_pll", pspec.__dict__["use_pll"])
+    print("debug", pspec.__dict__["debug"])
+
     dut = TestIssuer(pspec)
 
     vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")