versa_ecp5 adds ability to build and load for ulx3s85f, fixes testgpio

[soc.git] / src / soc / litex / florent / sim.py

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index d102b56de3ed089e3d3a5aafae74e4d811bc8281..d3687aa4515fa6ecaee22d406e59e50ac0f3bfba 100755 (executable)
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -32,7 +32,8 @@ SoCCSRHandler.supported_address_width.append(12)
 # LibreSoCSim -----------------------------------------------------------------
 
 class LibreSoCSim(SoCSDRAM):
-    def __init__(self, cpu="libresoc", debug=False, with_sdram=True,
+    def __init__(self, cpu="libresoc", variant="standardjtag", debug=False,
+            with_sdram=True,
             sdram_module          = "AS4C16M16",
             #sdram_data_width      = 16,
             #sdram_module          = "MT48LC16M16",
@@ -43,28 +44,20 @@ class LibreSoCSim(SoCSDRAM):
         platform     = Platform()
         sys_clk_freq = int(100e6)
 
-        #cpu_data_width = 32
-        cpu_data_width = 64
-
-        if cpu_data_width == 32:
-            variant = "standard32"
-        else:
-            variant = "standard"
-
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "hello_world/hello_world.bin"
-        ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
-                    "tests/3.bin"
+        #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+        #            "tests/1.bin"
         #ram_fname = "/tmp/test.bin"
-        #ram_fname = None
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "micropython/firmware.bin"
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "tests/xics/xics.bin"
-        ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
-                    "tests/decrementer/decrementer.bin"
+        #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+        #            "tests/decrementer/decrementer.bin"
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "hello_world/hello_world.bin"
+        ram_fname = None
 
         # reserve XICS ICP and XICS memory addresses.
         self.mem_map['icp'] = 0xc0004000
@@ -124,6 +117,7 @@ class LibreSoCSim(SoCSDRAM):
             ics_region = SoCRegion(origin=ics_addr, size=0x1000, cached=False)
             self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
 
+        if "gpio" in variant:
             # Simple GPIO peripheral
             gpio_addr = self.mem_map['gpio']
             gpio_wb = self.cpu.simple_gpio
@@ -164,6 +158,23 @@ class LibreSoCSim(SoCSDRAM):
             self.add_constant("MEMTEST_DATA_DEBUG", 1)
 
 
+        # add JTAG platform pins
+        platform.add_extension([
+            ("jtag", 0,
+                Subsignal("tck",  Pins(1)),
+                Subsignal("tms", Pins(1)),
+                Subsignal("tdi", Pins(1)),
+                Subsignal("tdo", Pins(1)),
+            )
+        ])
+
+        jtagpads = platform.request("jtag")
+        self.comb += self.cpu.jtag_tck.eq(jtagpads.tck)
+        self.comb += self.cpu.jtag_tms.eq(jtagpads.tms)
+        self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi)
+        self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo)
+
+
         # Debug ---------------------------------------------------------------
         if not debug:
             return
@@ -434,6 +445,8 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Sim")
     parser.add_argument("--cpu",          default="libresoc",
                         help="CPU to use: libresoc (default) or microwatt")
+    parser.add_argument("--variant",      default="standardjtag",
+                        help="Specify variant with different features")
     parser.add_argument("--debug",        action="store_true",
                         help="Enable debug traces")
     parser.add_argument("--trace",        action="store_true",
@@ -446,9 +459,10 @@ def main():
 
     sim_config = SimConfig(default_clk="sys_clk")
     sim_config.add_module("serial2console", "serial")
+    sim_config.add_module("jtagremote", "jtag", args={'port': 44853})
 
     for i in range(2):
-        soc = LibreSoCSim(cpu=args.cpu, debug=args.debug)
+        soc = LibreSoCSim(cpu=args.cpu, debug=args.debug, variant=args.variant)
         builder = Builder(soc,compile_gateware = i!=0)
         builder.build(sim_config=sim_config,
             run         = i!=0,