# DMI interface access
intrf = self.core.regs.rf['int']
+ fastrf = self.core.regs.rf['fast']
crrf = self.core.regs.rf['cr']
xerrf = self.core.regs.rf['xer']
- self.int_r = intrf.r_ports['dmi'] # INT read
- self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
- self.xer_r = xerrf.r_ports['full_xer'] # XER read
+ self.int_r = intrf.r_ports['dmi'] # INT DMI read
+ self.cr_r = crrf.r_ports['full_cr_dbg'] # CR DMI read
+ self.xer_r = xerrf.r_ports['full_xer'] # XER DMI read
+ self.fast_r = fastrf.r_ports['dmi'] # FAST DMI read
if self.svp64_en:
# for predication
# hack method of keeping an eye on whether branch/trap set the PC
self.state_nia = self.core.regs.rf['state'].w_ports['nia']
self.state_nia.wen.name = 'state_nia_wen'
+ # and whether SPR pipeline sets DEC or TB
+ self.state_spr = self.core.regs.rf['state'].w_ports['state1']
# pulse to synchronize the simulator at instruction end
self.insn_done = Signal()
# this is for verilator debug purposes
if self.microwatt_compat:
self.nia = Signal(64)
+ self.msr_o = Signal(64)
self.nia_req = Signal(1)
self.insn = Signal(32)
+ self.ldst_req = Signal(1)
+ self.ldst_addr = Signal(1)
+
+ # for pausing dec/tb during an SPR pipeline event, this
+ # ensures that an SPR write (mtspr) to TB or DEC does not
+ # get overwritten by the DEC/TB FSM
+ self.pause_dec_tb = Signal()
def setup_peripherals(self, m):
comb, sync = m.d.comb, m.d.sync
m.submodules.core = core = self.core
else:
m.submodules.core = core = csd(self.core)
+
# this _so_ needs sorting out. ICache is added down inside
# LoadStore1 and is already a submodule of LoadStore1
if not isinstance(self.imem, ICache):
m.submodules.imem = imem = csd(self.imem)
+
+ # set up JTAG Debug Module (in correct domain)
m.submodules.dbg = dbg = dbd(self.dbg)
if self.jtag_en:
m.submodules.jtag = jtag = dbd(self.jtag)
dbus = self.core.l0.cmpi.wb_bus()
comb += self.ibus_adr.eq(Cat(Const(0, 3), ibus.adr))
comb += self.dbus_adr.eq(Cat(Const(0, 3), dbus.adr))
+ # microwatt verilator debug purposes
+ pi = self.core.l0.cmpi.pi.pi
+ comb += self.ldst_req.eq(pi.addr_ok_o)
+ comb += self.ldst_addr.eq(pi.addr)
cur_state = self.cur_state
if self.svp64_en:
m.submodules.svp64 = svp64 = csd(self.svp64)
- # convenience
- dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
- intrf = self.core.regs.rf['int']
-
# clock delay power-on reset
cd_por = ClockDomain(reset_less=True)
cd_sync = ClockDomain()
dbg_sync = ClockDomain(self.dbg_domain)
m.domains += dbg_sync
+ # create a delay, but remember it is in the power-on-reset clock domain!
ti_rst = Signal(reset_less=True)
delay = Signal(range(4), reset=3)
+ stop_delay = Signal(range(16), reset=5)
with m.If(delay != 0):
- m.d.por += delay.eq(delay - 1)
+ m.d.por += delay.eq(delay - 1) # decrement... in POR domain!
+ with m.If(stop_delay != 0):
+ m.d.por += stop_delay.eq(stop_delay - 1) # likewise
comb += cd_por.clk.eq(ClockSignal())
# power-on reset delay
else:
with m.If(delay != 0 | dbg.core_rst_o):
comb += core_rst.eq(1)
+ with m.If(stop_delay != 0):
+ # run DMI core-stop as well but on an extra couple of cycles
+ comb += dbg.core_stopped_i.eq(1)
# connect external reset signal to DMI Reset
if self.dbg_domain != "sync":
comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
# temporary hack: says "go" immediately for both address gen and ST
+ # XXX: st.go_i is set to 1 cycle delay to reduce combinatorial chains
l0 = core.l0
ldst = core.fus.fus['ldst0']
st_go_edge = rising_edge(m, ldst.st.rel_o)
# link addr-go direct to rel
m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o)
- m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
+ m.d.sync += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
def do_dmi(self, m, dbg):
"""deals with DMI debug requests
comb = m.d.comb
sync = m.d.sync
dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
+ d_fast = dbg.d_fast
intrf = self.core.regs.rf['int']
+ fastrf = self.core.regs.rf['fast']
with m.If(d_reg.req): # request for regfile access being made
# TODO: error-check this
comb += d_reg.data.eq(self.int_r.o_data)
comb += d_reg.ack.eq(1)
+ # fast regfile
+ with m.If(d_fast.req): # request for regfile access being made
+ if fastrf.unary:
+ comb += self.fast_r.ren.eq(1 << d_fast.addr)
+ else:
+ comb += self.fast_r.addr.eq(d_fast.addr)
+ comb += self.fast_r.ren.eq(1)
+ d_fast_delay = Signal()
+ sync += d_fast_delay.eq(d_fast.req)
+ with m.If(d_fast_delay):
+ # data arrives one clock later
+ comb += d_fast.data.eq(self.fast_r.o_data)
+ comb += d_fast.ack.eq(1)
+
# sigh same thing for CR debug
with m.If(d_cr.req): # request for regfile access being made
comb += self.cr_r.ren.eq(0b11111111) # enable all
value to DEC, however the regfile has "passthrough" on it so this
*should* be ok.
- see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
+ see v3.0B p1097-1099 for Timer Resource and p1065 and p1076
"""
comb, sync = m.d.comb, m.d.sync
- fast_rf = self.core.regs.rf['fast']
- fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
- fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
+ state_rf = self.core.regs.rf['state']
+ state_r_dectb = state_rf.r_ports['issue'] # DEC/TB
+ state_w_dectb = state_rf.w_ports['issue'] # DEC/TB
with m.FSM() as fsm:
# initiates read of current DEC
with m.State("DEC_READ"):
- comb += fast_r_dectb.addr.eq(FastRegs.DEC)
- comb += fast_r_dectb.ren.eq(1)
- m.next = "DEC_WRITE"
+ comb += state_r_dectb.ren.eq(1<<StateRegs.DEC)
+ with m.If(~self.pause_dec_tb):
+ m.next = "DEC_WRITE"
# waits for DEC read to arrive (1 cycle), updates with new value
+ # respects if dec/tb writing has been paused
with m.State("DEC_WRITE"):
- new_dec = Signal(64)
- # TODO: MSR.LPCR 32-bit decrement mode
- comb += new_dec.eq(fast_r_dectb.o_data - 1)
- comb += fast_w_dectb.addr.eq(FastRegs.DEC)
- comb += fast_w_dectb.wen.eq(1)
- comb += fast_w_dectb.i_data.eq(new_dec)
- sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
- m.next = "TB_READ"
+ with m.If(self.pause_dec_tb):
+ # if paused, return to reading
+ m.next = "DEC_READ"
+ with m.Else():
+ new_dec = Signal(64)
+ # TODO: MSR.LPCR 32-bit decrement mode
+ comb += new_dec.eq(state_r_dectb.o_data - 1)
+ comb += state_w_dectb.wen.eq(1<<StateRegs.DEC)
+ comb += state_w_dectb.i_data.eq(new_dec)
+ # copy to cur_state for decoder, for an interrupt
+ sync += spr_dec.eq(new_dec)
+ m.next = "TB_READ"
# initiates read of current TB
with m.State("TB_READ"):
- comb += fast_r_dectb.addr.eq(FastRegs.TB)
- comb += fast_r_dectb.ren.eq(1)
- m.next = "TB_WRITE"
+ comb += state_r_dectb.ren.eq(1<<StateRegs.TB)
+ with m.If(~self.pause_dec_tb):
+ m.next = "TB_WRITE"
# waits for read TB to arrive, initiates write of current TB
+ # respects if dec/tb writing has been paused
with m.State("TB_WRITE"):
- new_tb = Signal(64)
- comb += new_tb.eq(fast_r_dectb.o_data + 1)
- comb += fast_w_dectb.addr.eq(FastRegs.TB)
- comb += fast_w_dectb.wen.eq(1)
- comb += fast_w_dectb.i_data.eq(new_tb)
- m.next = "DEC_READ"
+ with m.If(self.pause_dec_tb):
+ # if paused, return to reading
+ m.next = "TB_READ"
+ with m.Else():
+ new_tb = Signal(64)
+ comb += new_tb.eq(state_r_dectb.o_data + 1)
+ comb += state_w_dectb.wen.eq(1<<StateRegs.TB)
+ comb += state_w_dectb.i_data.eq(new_tb)
+ m.next = "DEC_READ"
return m
# reset current state if core reset requested
with m.If(core_rst):
m.d.sync += self.cur_state.eq(0)
+ # and, sigh, set configured values, which are also done in regfile
+ m.d.sync += self.cur_state.pc.eq(self.core.pc_at_reset)
+ m.d.sync += self.cur_state.msr.eq(self.core.msr_at_reset)
# check halted condition: requested PC to execute matches DMI stop addr
# and immediately stop. address of 0xffff_ffff_ffff_ffff can never
ports = [self.core.o.core_terminate_o,
self.ext_irq,
self.alt_reset, # not connected yet
- self.nia, self.insn, self.nia_req,
+ self.nia, self.insn, self.nia_req, self.msr_o,
+ self.ldst_req, self.ldst_addr,
ClockSignal(),
ResetSignal(),
]
easy understanding) come later.
"""
- def fetch_fsm(self, m, dbg, core, pc, msr, svstate, nia, is_svp64_mode,
+ def fetch_fsm(self, m, dbg, core, nia, is_svp64_mode,
fetch_pc_o_ready, fetch_pc_i_valid,
fetch_insn_o_valid, fetch_insn_i_ready):
"""fetch FSM
pdecode2 = self.pdecode2
cur_state = self.cur_state
dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
+ pc, msr, svstate = cur_state.pc, cur_state.msr, cur_state.svstate
# also note instruction fetch failed
if hasattr(core, "icache"):
with m.FSM(name='fetch_fsm'):
+ # allow fetch to not run at startup due to I-Cache reset not
+ # having time to settle. power-on-reset holds dbg.core_stopped_i
+ with m.State("PRE_IDLE"):
+ with m.If(~dbg.core_stopped_i & ~dbg.core_stop_o):
+ m.next = "IDLE"
+
# waiting (zzz)
with m.State("IDLE"):
# fetch allowed if not failed and stopped but not stepping
comb += self.imem.a_pc_i.eq(pc)
comb += self.imem.a_i_valid.eq(1)
comb += self.imem.f_i_valid.eq(1)
- # transfer state to output
- sync += cur_state.pc.eq(pc)
- sync += cur_state.svstate.eq(svstate) # and svstate
- sync += cur_state.msr.eq(msr) # and msr
-
m.next = "INSN_READ" # move to "wait for bus" phase
# dummy pause to find out why simulation is not keeping up
# for verilator debug purposes
comb += self.insn.eq(insn)
comb += self.nia.eq(cur_state.pc)
+ comb += self.msr_o.eq(cur_state.msr)
comb += self.nia_req.eq(1)
m.next = "INSN_READY"
fetch_failed = Const(0, 1)
flush_needed = False
+ sync += fetch_pc_i_valid.eq(0)
+
with m.FSM(name="issue_fsm"):
# sync with the "fetch" phase which is reading the instruction
# wait on "core stop" release, before next fetch
# need to do this here, in case we are in a VL==0 loop
with m.If(~dbg.core_stop_o & ~core_rst):
- comb += fetch_pc_i_valid.eq(1) # tell fetch to start
+ sync += fetch_pc_i_valid.eq(1) # tell fetch to start
+ sync += cur_state.pc.eq(dbg.state.pc)
+ sync += cur_state.svstate.eq(dbg.state.svstate)
+ sync += cur_state.msr.eq(dbg.state.msr)
with m.If(fetch_pc_o_ready): # fetch acknowledged us
m.next = "INSN_WAIT"
with m.Else():
# instruction started: must wait till it finishes
with m.State("INSN_ACTIVE"):
- # note changes to MSR, PC and SVSTATE
- # XXX oops, really must monitor *all* State Regfile write
- # ports looking for changes!
+ # note changes to MSR, PC and SVSTATE, and DEC/TB
+ # these last two are done together, and passed to the
+ # DEC/TB FSM
with m.If(self.state_nia.wen & (1 << StateRegs.SVSTATE)):
sync += self.sv_changed.eq(1)
with m.If(self.state_nia.wen & (1 << StateRegs.MSR)):
sync += self.msr_changed.eq(1)
with m.If(self.state_nia.wen & (1 << StateRegs.PC)):
sync += self.pc_changed.eq(1)
+ with m.If((self.state_spr.wen &
+ ((1 << StateRegs.DEC) | (1 << StateRegs.TB))).bool()):
+ comb += self.pause_dec_tb.eq(1)
with m.If(~core_busy_o): # instruction done!
comb += exec_pc_o_valid.eq(1)
with m.If(exec_pc_i_ready):
# Issue is where the VL for-loop # lives. the ready/valid
# signalling is used to communicate between the four.
- self.fetch_fsm(m, dbg, core, dbg.state.pc, dbg.state.msr,
- dbg.state.svstate, nia, is_svp64_mode,
+ self.fetch_fsm(m, dbg, core, nia, is_svp64_mode,
fetch_pc_o_ready, fetch_pc_i_valid,
fetch_insn_o_valid, fetch_insn_i_ready)
}
pspec = TestMemPspec(ldst_ifacetype='bare_wb',
imem_ifacetype='bare_wb',
- addr_wid=48,
+ addr_wid=64,
mask_wid=8,
reg_wid=64,
units=units)