Support debug system bus access.

[riscv-isa-sim.git] / tests / ebreak.py

diff --git a/tests/ebreak.py b/tests/ebreak.py
index 4b41f7db4fce20ba6b820f77b4227f1a9e354326..dd7e65878b7a9f19dc0e9634d7bb24c385fc8de7 100755 (executable)
--- a/tests/ebreak.py
+++ b/tests/ebreak.py
@@ -12,13 +12,13 @@ class EbreakTest(unittest.TestCase):
 
     def test_noport(self):
         """Make sure that we can run past ebreak when --gdb-port isn't used."""
-        spike = testlib.spike(self.binary, with_gdb=False, timeout=10)
+        spike = testlib.Spike(self.binary, with_gdb=False, timeout=10)
         result = spike.wait()
         self.assertEqual(result, 0)
 
     def test_nogdb(self):
         """Make sure that we can run past ebreak when gdb isn't attached."""
-        spike, port = testlib.spike(self.binary, timeout=10)
+        spike = testlib.Spike(self.binary, timeout=10)
         result = spike.wait()
         self.assertEqual(result, 0)