Do a better job checking CSR functionality.

[riscv-isa-sim.git] / tests / regs.s

diff --git a/tests/regs.s b/tests/regs.s
index b0d641d9d937963cf14a7222d9d20bd17c3f9b27..e6456e14111a329aabedc4a4467f90d98c8ccf74 100644 (file)
--- a/tests/regs.s
+++ b/tests/regs.s
@@ -3,7 +3,6 @@ main:
         j       main
 
 write_regs:
-        la      a0, data
         sd      x1, 0(a0)
         sd      x2, 8(a0)
         sd      x3, 16(a0)
@@ -35,6 +34,8 @@ write_regs:
         sd      x30, 224(a0)
         sd      x31, 232(a0)
 
+        csrr    x1, 1   # fflags
+
 all_done:
         j       all_done