wide interface, we can contract SymbioticEDA to *design* a DDR3 PHY for us,
which both we *and the rest of the worldwide Silicon Community can use
without limitation* because we will ask SymbioticEDA to make the design
-libre-licensed, for anyone to use.
+(and layout) libre-licensed, for anyone to use.
USD 250,000 pays for the mask charges that will allow us to do the 40nm
quad-core ASIC that we have on the roadmap for the second chip. USD
the extremely simple and highly effective hardware but timing-critical
design aspects of the circular loops in the 6600 were recognised by James
Thornton (the co-designer of the 6600) as being paradoxically challenging
-to understand why so few gates could be so effective. Consequently,
-documenting it just to be able to *develop* it is extremely important.
+to understand why so few gates could be so effective (being as they were,
+literally the world's first ever out-of-order superscalar architecture).
+Consequently, documenting it just to be able to *develop* it is extremely
+important.
We're getting to the point where we need to connect the LOAD/STORE Computation
Units up to an actual memory architecture. We've chosen
(Staf is also [sponsored by NLNet](https://nlnet.nl/project/Chips4Makers/)
to create Libre-licensed Cell Libraries, busting through one of the -
-many - layers of NDAs and reducing NREs for ASIC development: I helped him
-put in the submission, and he was really happy to do the Cell Libraries
-that we will be using for LibreSOC's 180nm test tape-out in October 2020.)
+many - layers of NDAs and reducing NREs and unnecessary and artificial
+barriers for ASIC development: I helped him put in the submission, and
+he was really happy to do the Cell Libraries that we will be using for
+LibreSOC's 180nm test tape-out in October 2020.)
# Public-Inbox and Domain Migration