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add load/store misaligned
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sun, 25 Nov 2018 01:56:05 +0000
(
01:56
+0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sun, 25 Nov 2018 01:56:05 +0000
(
01:56
+0000)
cpu.py
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diff --git
a/cpu.py
b/cpu.py
index ed3c450096966525d936ccb813dcfe71df8c9a91..a975d8ec6d5426a73d6df5b426add1f7ba579a8c 100644
(file)
--- a/
cpu.py
+++ b/
cpu.py
@@
-163,6
+163,20
@@
class CPU(Module):
self.comb += load_store_address_low_2.eq(
decoder_immediate[:2] + register_rs1[:2])
self.comb += load_store_address_low_2.eq(
decoder_immediate[:2] + register_rs1[:2])
+ load_store_misaligned = Signal()
+
+ lsa = self.get_ls_misaligned(load_store_misaligned, decoder_funct3,
+ load_store_address_low_2)
+ self.comb += lsa
+
+ def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
+ return Case(funct3[:2],
+ { F3.sb: ls.eq(Constant(0)),
+ F3.sh: ls.eq(load_store_address_low_2[0] != 0),
+ F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
+ "default": ls.eq(Constant(1))
+ })
+
if __name__ == "__main__":
example = CPU()
if __name__ == "__main__":
example = CPU()