add CPU decoder instance

diff --git a/cpu.py b/cpu.py
index 1e83db0abd07ee4c337893c1e8ab0deb07e22bd0..ed3c450096966525d936ccb813dcfe71df8c9a91 100644 (file)
--- a/cpu.py
+++ b/cpu.py
@@ -58,15 +58,15 @@ class CPU(Module):
         l = []
         for i in range(31):
             l.append(Signal(32, name="register%d" % i))
         l = []
         for i in range(31):
             l.append(Signal(32, name="register%d" % i))

-        self.registers = Array(l)
+        registers = Array(l)

 
         #self.sync += self.registers[0].eq(0)
         #self.sync += self.registers[1].eq(0)
 
 
         #self.sync += self.registers[0].eq(0)
         #self.sync += self.registers[1].eq(0)
 

-        memory_interface_fetch_address = Signal(32)[2:]
+        memory_interface_fetch_address = Signal(32) # XXX [2:]

         memory_interface_fetch_data = Signal(32)
         memory_interface_fetch_valid = Signal()
         memory_interface_fetch_data = Signal(32)
         memory_interface_fetch_valid = Signal()

-        memory_interface_rw_address= Signal(32)[2:]
+        memory_interface_rw_address= Signal(32) # XXX [2:]

         memory_interface_rw_byte_mask = Signal(4)
         memory_interface_rw_read_not_write = Signal()
         memory_interface_rw_active = Signal()
         memory_interface_rw_byte_mask = Signal(4)
         memory_interface_rw_read_not_write = Signal()
         memory_interface_rw_active = Signal()


@@ -75,7 +75,7 @@ class CPU(Module):
         memory_interface_rw_address_valid = Signal()
         memory_interface_rw_wait = Signal()
 
         memory_interface_rw_address_valid = Signal()
         memory_interface_rw_wait = Signal()
 

-        mi = Instance("cpu_memory_interface",
+        mi = Instance("cpu_memory_interface", name="memory_instance",

                     p_ram_size = ram_size,
                     p_ram_start = ram_start,
                     i_clk=ClockSignal(),
                     p_ram_size = ram_size,
                     p_ram_start = ram_start,
                     i_clk=ClockSignal(),


@@ -107,7 +107,7 @@ class CPU(Module):
         fetch_output_instruction = Signal(32)
         fetch_output_st = Signal(fetch_output_state)
 
         fetch_output_instruction = Signal(32)
         fetch_output_st = Signal(fetch_output_state)
 

-        fs = Instance("CPUFetchStage",
+        fs = Instance("CPUFetchStage", name="fetch_stage",

             i_clk=ClockSignal(),
             i_rst=ResetSignal(),
             o_memory_interface_fetch_address = memory_interface_fetch_address,
             i_clk=ClockSignal(),
             i_rst=ResetSignal(),
             o_memory_interface_fetch_address = memory_interface_fetch_address,


@@ -123,6 +123,47 @@ class CPU(Module):
         )
         self.specials += fs
 
         )
         self.specials += fs
 

+        decoder_funct7 = Signal(7)
+        decoder_funct3 = Signal(3)
+        decoder_rd = Signal(5)
+        decoder_rs1 = Signal(5)
+        decoder_rs2 = Signal(5)
+        decoder_immediate = Signal(32)
+        decoder_opcode = Signal(7)
+        decode_act = Signal(decode_action)
+
+        cd = Instance("CPUDecoder", name="decoder",
+            i_instruction = fetch_output_instruction,
+            o_funct7 = decoder_funct7,
+            o_funct3 = decoder_funct3,
+            o_rd = decoder_rd,
+            o_rs1 = decoder_rs1,
+            o_rs2 = decoder_rs2,
+            o_immediate = decoder_immediate,
+            o_opcode = decoder_opcode,
+            o_decode_action = decode_act
+        )
+        self.specials += cd
+
+        register_rs1 = Signal(32)
+        register_rs2 = Signal(32)
+        self.comb += If(decoder_rs1 == 0,
+                        register_rs1.eq(0)
+                     ).Else(
+                        register_rs1.eq(registers[decoder_rs1-1]))
+        self.comb += If(decoder_rs2 == 0,
+                        register_rs2.eq(0)
+                     ).Else(
+                        register_rs2.eq(registers[decoder_rs2-1]))
+
+        load_store_address = Signal(32)
+        load_store_address_low_2 = Signal(2)
+
+        self.comb += load_store_address.eq(decoder_immediate + register_rs1)
+        self.comb += load_store_address_low_2.eq(
+                            decoder_immediate[:2] + register_rs1[:2])
+
+

 if __name__ == "__main__":
     example = CPU()
     print(verilog.convert(example,
 if __name__ == "__main__":
     example = CPU()
     print(verilog.convert(example,


@@ -137,54 +178,6 @@ if __name__ == "__main__":
            }))
 
 """
            }))
 
 """

-    wire `fetch_action fetch_action;
-    wire [31:0] fetch_target_pc;
-    wire [31:0] fetch_output_pc;
-    wire [31:0] fetch_output_instruction;
-    wire `fetch_output_state fetch_output_state;
-
-    cpu_fetch_stage #(
-        .reset_vector(reset_vector),
-        .mtvec(mtvec)
-        ) fetch_stage(
-        .clk(clk),
-        .reset(reset),
-        .memory_interface_fetch_address(memory_interface_fetch_address),
-        .memory_interface_fetch_data(memory_interface_fetch_data),
-        .memory_interface_fetch_valid(memory_interface_fetch_valid),
-        .fetch_action(fetch_action),
-        .target_pc(fetch_target_pc),
-        .output_pc(fetch_output_pc),
-        .output_instruction(fetch_output_instruction),
-        .output_state(fetch_output_state)
-        );
-
-    wire [6:0] decoder_funct7;
-    wire [2:0] decoder_funct3;
-    wire [4:0] decoder_rd;
-    wire [4:0] decoder_rs1;
-    wire [4:0] decoder_rs2;
-    wire [31:0] decoder_immediate;
-    wire [6:0] decoder_opcode;
-    wire `decode_action decode_action;
-
-    cpu_decoder decoder(
-        .instruction(fetch_output_instruction),
-        .funct7(decoder_funct7),
-        .funct3(decoder_funct3),
-        .rd(decoder_rd),
-        .rs1(decoder_rs1),
-        .rs2(decoder_rs2),
-        .immediate(decoder_immediate),
-        .opcode(decoder_opcode),
-        .decode_action(decode_action));
-
-    wire [31:0] register_rs1 = (decoder_rs1 == 0) ? 0 : registers[decoder_rs1];
-    wire [31:0] register_rs2 = (decoder_rs2 == 0) ? 0 : registers[decoder_rs2];
-
-    wire [31:0] load_store_address = decoder_immediate + register_rs1;
-
-    wire [1:0] load_store_address_low_2 = decoder_immediate[1:0] + register_rs1[1:0];

 
     function get_load_store_misaligned(
         input [2:0] funct3,
 
     function get_load_store_misaligned(
         input [2:0] funct3,