cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 from migen import *
  30 from migen.fhdl import verilog
  31
  32 from riscvdefs import *
  33 from cpudefs import *
  34
  35 class CPU(Module):
  36     """
  37     """
  38
  39     def __init__(self):
  40         #self.clk = ClockSignal()
  41         #self.reset = ResetSignal()
  42         self.tty_write = Signal()
  43         self.tty_write_data = Signal(8)
  44         self.tty_write_busy = Signal()
  45         self.switch_2 = Signal()
  46         self.switch_3 = Signal()
  47         self.led_1 = Signal()
  48         self.led_3 = Signal()
  49
  50         ram_size = Constant(0x8000)
  51         ram_start = Constant(0x10000, 32)
  52         reset_vector = Signal(32)
  53         mtvec = Signal(32)
  54
  55         reset_vector.eq(ram_start)
  56         mtvec.eq(ram_start + 0x40)
  57
  58         l = []
  59         for i in range(31):
  60             l.append(Signal(32, name="register%d" % i))
  61         self.registers = Array(l)
  62
  63         #self.sync += self.registers[0].eq(0)
  64         #self.sync += self.registers[1].eq(0)
  65
  66         memory_interface_fetch_address = Signal(32)[2:]
  67         memory_interface_fetch_data = Signal(32)
  68         memory_interface_fetch_valid = Signal()
  69         memory_interface_rw_address= Signal(32)[2:]
  70         memory_interface_rw_byte_mask = Signal(4)
  71         memory_interface_rw_read_not_write = Signal()
  72         memory_interface_rw_active = Signal()
  73         memory_interface_rw_data_in = Signal(32)
  74         memory_interface_rw_data_out = Signal(32)
  75         memory_interface_rw_address_valid = Signal()
  76         memory_interface_rw_wait = Signal()
  77
  78         mi = Instance("cpu_memory_interface",
  79                     p_ram_size = ram_size,
  80                     p_ram_start = ram_start,
  81                     i_clk=ClockSignal(),
  82                     i_rst=ResetSignal(),
  83                     i_fetch_address = memory_interface_fetch_address,
  84                     o_fetch_data = memory_interface_fetch_data,
  85                     o_fetch_valid = memory_interface_fetch_valid,
  86                     i_rw_address = memory_interface_rw_address,
  87                     i_rw_byte_mask = memory_interface_rw_byte_mask,
  88                     i_rw_read_not_write = memory_interface_rw_read_not_write,
  89                     i_rw_active = memory_interface_rw_active,
  90                     i_rw_data_in = memory_interface_rw_data_in,
  91                     o_rw_data_out = memory_interface_rw_data_out,
  92                     o_rw_address_valid = memory_interface_rw_address_valid,
  93                     o_rw_wait = memory_interface_rw_wait,
  94                     o_tty_write = self.tty_write,
  95                     o_tty_write_data = self.tty_write_data,
  96                     i_tty_write_busy = self.tty_write_busy,
  97                     i_switch_2 = self.switch_2,
  98                     i_switch_3 = self.switch_3,
  99                     o_led_1 = self.led_1,
 100                     o_led_3 = self.led_3
 101                   )
 102         self.specials += mi
 103
 104         fetch_act = Signal(fetch_action)
 105         fetch_target_pc = Signal(32)
 106         fetch_output_pc = Signal(32)
 107         fetch_output_instruction = Signal(32)
 108         fetch_output_st = Signal(fetch_output_state)
 109
 110         fs = Instance("CPUFetchStage",
 111             i_clk=ClockSignal(),
 112             i_rst=ResetSignal(),
 113             o_memory_interface_fetch_address = memory_interface_fetch_address,
 114             i_memory_interface_fetch_data = memory_interface_fetch_data,
 115             i_memory_interface_fetch_valid = memory_interface_fetch_valid,
 116             i_fetch_action = fetch_act,
 117             i_target_pc = fetch_target_pc,
 118             o_output_pc = fetch_output_pc,
 119             o_output_instruction = fetch_output_instruction,
 120             o_output_state = fetch_output_st,
 121             i_reset_vector = reset_vector,
 122             i_mtvec = mtvec,
 123         )
 124         self.specials += fs
 125
 126 if __name__ == "__main__":
 127     example = CPU()
 128     print(verilog.convert(example,
 129          {
 130            example.tty_write,
 131            example.tty_write_data,
 132            example.tty_write_busy,
 133            example.switch_2,
 134            example.switch_3,
 135            example.led_1,
 136            example.led_3,
 137            }))
 138
 139 """
 140     wire `fetch_action fetch_action;
 141     wire [31:0] fetch_target_pc;
 142     wire [31:0] fetch_output_pc;
 143     wire [31:0] fetch_output_instruction;
 144     wire `fetch_output_state fetch_output_state;
 145
 146     cpu_fetch_stage #(
 147         .reset_vector(reset_vector),
 148         .mtvec(mtvec)
 149         ) fetch_stage(
 150         .clk(clk),
 151         .reset(reset),
 152         .memory_interface_fetch_address(memory_interface_fetch_address),
 153         .memory_interface_fetch_data(memory_interface_fetch_data),
 154         .memory_interface_fetch_valid(memory_interface_fetch_valid),
 155         .fetch_action(fetch_action),
 156         .target_pc(fetch_target_pc),
 157         .output_pc(fetch_output_pc),
 158         .output_instruction(fetch_output_instruction),
 159         .output_state(fetch_output_state)
 160         );
 161
 162     wire [6:0] decoder_funct7;
 163     wire [2:0] decoder_funct3;
 164     wire [4:0] decoder_rd;
 165     wire [4:0] decoder_rs1;
 166     wire [4:0] decoder_rs2;
 167     wire [31:0] decoder_immediate;
 168     wire [6:0] decoder_opcode;
 169     wire `decode_action decode_action;
 170
 171     cpu_decoder decoder(
 172         .instruction(fetch_output_instruction),
 173         .funct7(decoder_funct7),
 174         .funct3(decoder_funct3),
 175         .rd(decoder_rd),
 176         .rs1(decoder_rs1),
 177         .rs2(decoder_rs2),
 178         .immediate(decoder_immediate),
 179         .opcode(decoder_opcode),
 180         .decode_action(decode_action));
 181
 182     wire [31:0] register_rs1 = (decoder_rs1 == 0) ? 0 : registers[decoder_rs1];
 183     wire [31:0] register_rs2 = (decoder_rs2 == 0) ? 0 : registers[decoder_rs2];
 184
 185     wire [31:0] load_store_address = decoder_immediate + register_rs1;
 186
 187     wire [1:0] load_store_address_low_2 = decoder_immediate[1:0] + register_rs1[1:0];
 188
 189     function get_load_store_misaligned(
 190         input [2:0] funct3,
 191         input [1:0] load_store_address_low_2
 192         );
 193     begin
 194         case(funct3[1:0])
 195         `funct3_sb:
 196             get_load_store_misaligned = 0;
 197         `funct3_sh:
 198             get_load_store_misaligned = load_store_address_low_2[0] != 0;
 199         `funct3_sw:
 200             get_load_store_misaligned = load_store_address_low_2[1:0] != 0;
 201         default:
 202             get_load_store_misaligned = 1'bX;
 203         endcase
 204     end
 205     endfunction
 206
 207     wire load_store_misaligned = get_load_store_misaligned(decoder_funct3, load_store_address_low_2);
 208
 209     assign memory_interface_rw_address = load_store_address[31:2];
 210
 211     wire [3:0] unshifted_load_store_byte_mask = {decoder_funct3[1] ? 2'b11 : 2'b00, (decoder_funct3[1] | decoder_funct3[0]) ? 1'b1 : 1'b0, 1'b1};
 212
 213     assign memory_interface_rw_byte_mask = unshifted_load_store_byte_mask << load_store_address_low_2;
 214
 215     assign memory_interface_rw_data_in[31:24] = load_store_address_low_2[1]
 216                                                 ? (load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8])
 217                                                 : (load_store_address_low_2[0] ? register_rs2[23:16] : register_rs2[31:24]);
 218     assign memory_interface_rw_data_in[23:16] = load_store_address_low_2[1] ? register_rs2[7:0] : register_rs2[23:16];
 219     assign memory_interface_rw_data_in[15:8] = load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8];
 220     assign memory_interface_rw_data_in[7:0] = register_rs2[7:0];
 221
 222     wire [31:0] unmasked_loaded_value;
 223
 224     assign unmasked_loaded_value[7:0] = load_store_address_low_2[1]
 225                                         ? (load_store_address_low_2[0] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[23:16])
 226                                         : (load_store_address_low_2[0] ? memory_interface_rw_data_out[15:8] : memory_interface_rw_data_out[7:0]);
 227     assign unmasked_loaded_value[15:8] = load_store_address_low_2[1] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[15:8];
 228     assign unmasked_loaded_value[31:16] = memory_interface_rw_data_out[31:16];
 229
 230     wire [31:0] loaded_value;
 231
 232     assign loaded_value[7:0] = unmasked_loaded_value[7:0];
 233     assign loaded_value[15:8] = decoder_funct3[1:0] == 0 ? ({8{~decoder_funct3[2] & unmasked_loaded_value[7]}}) : unmasked_loaded_value[15:8];
 234     assign loaded_value[31:16] = decoder_funct3[1] == 0 ? ({16{~decoder_funct3[2] & (decoder_funct3[0] ? unmasked_loaded_value[15] : unmasked_loaded_value[7])}}) : unmasked_loaded_value[31:16];
 235
 236     assign memory_interface_rw_active = ~reset
 237                                         & (fetch_output_state == `fetch_output_state_valid)
 238                                         & ~load_store_misaligned
 239                                         & ((decode_action & (`decode_action_load | `decode_action_store)) != 0);
 240
 241     assign memory_interface_rw_read_not_write = ~decoder_opcode[5];
 242
 243     wire [31:0] alu_a = register_rs1;
 244     wire [31:0] alu_b = decoder_opcode[5] ? register_rs2 : decoder_immediate;
 245     wire [31:0] alu_result;
 246
 247     cpu_alu alu(
 248         .funct7(decoder_funct7),
 249         .funct3(decoder_funct3),
 250         .opcode(decoder_opcode),
 251         .a(alu_a),
 252         .b(alu_b),
 253         .result(alu_result)
 254         );
 255
 256     wire [31:0] lui_auipc_result = decoder_opcode[5] ? decoder_immediate : decoder_immediate + fetch_output_pc;
 257
 258     assign fetch_target_pc[31:1] = ((decoder_opcode != `opcode_jalr ? fetch_output_pc[31:1] : register_rs1[31:1]) + decoder_immediate[31:1]);
 259     assign fetch_target_pc[0] = 0;
 260
 261     wire misaligned_jump_target = fetch_target_pc[1];
 262
 263     wire [31:0] branch_arg_a = {register_rs1[31] ^ ~decoder_funct3[1], register_rs1[30:0]};
 264     wire [31:0] branch_arg_b = {register_rs2[31] ^ ~decoder_funct3[1], register_rs2[30:0]};
 265
 266     wire branch_taken = decoder_funct3[0] ^ (decoder_funct3[2] ? branch_arg_a < branch_arg_b : branch_arg_a == branch_arg_b);
 267
 268     reg [31:0] mcause = 0;
 269     reg [31:0] mepc = 32'hXXXXXXXX;
 270     reg [31:0] mscratch = 32'hXXXXXXXX;
 271
 272     reg mstatus_mpie = 1'bX;
 273     reg mstatus_mie = 0;
 274     parameter mstatus_mprv = 0;
 275     parameter mstatus_tsr = 0;
 276     parameter mstatus_tw = 0;
 277     parameter mstatus_tvm = 0;
 278     parameter mstatus_mxr = 0;
 279     parameter mstatus_sum = 0;
 280     parameter mstatus_xs = 0;
 281     parameter mstatus_fs = 0;
 282     parameter mstatus_mpp = 2'b11;
 283     parameter mstatus_spp = 0;
 284     parameter mstatus_spie = 0;
 285     parameter mstatus_upie = 0;
 286     parameter mstatus_sie = 0;
 287     parameter mstatus_uie = 0;
 288
 289     reg mie_meie = 1'bX;
 290     reg mie_mtie = 1'bX;
 291     reg mie_msie = 1'bX;
 292     parameter mie_seie = 0;
 293     parameter mie_ueie = 0;
 294     parameter mie_stie = 0;
 295     parameter mie_utie = 0;
 296     parameter mie_ssie = 0;
 297     parameter mie_usie = 0;
 298
 299     task reset_to_initial;
 300     begin
 301         mcause = 0;
 302         mepc = 32'hXXXXXXXX;
 303         mscratch = 32'hXXXXXXXX;
 304         mstatus_mie = 0;
 305         mstatus_mpie = 1'bX;
 306         mie_meie = 1'bX;
 307         mie_mtie = 1'bX;
 308         mie_msie = 1'bX;
 309         registers['h01] <= 32'hXXXXXXXX;
 310         registers['h02] <= 32'hXXXXXXXX;
 311         registers['h03] <= 32'hXXXXXXXX;
 312         registers['h04] <= 32'hXXXXXXXX;
 313         registers['h05] <= 32'hXXXXXXXX;
 314         registers['h06] <= 32'hXXXXXXXX;
 315         registers['h07] <= 32'hXXXXXXXX;
 316         registers['h08] <= 32'hXXXXXXXX;
 317         registers['h09] <= 32'hXXXXXXXX;
 318         registers['h0A] <= 32'hXXXXXXXX;
 319         registers['h0B] <= 32'hXXXXXXXX;
 320         registers['h0C] <= 32'hXXXXXXXX;
 321         registers['h0D] <= 32'hXXXXXXXX;
 322         registers['h0E] <= 32'hXXXXXXXX;
 323         registers['h0F] <= 32'hXXXXXXXX;
 324         registers['h10] <= 32'hXXXXXXXX;
 325         registers['h11] <= 32'hXXXXXXXX;
 326         registers['h12] <= 32'hXXXXXXXX;
 327         registers['h13] <= 32'hXXXXXXXX;
 328         registers['h14] <= 32'hXXXXXXXX;
 329         registers['h15] <= 32'hXXXXXXXX;
 330         registers['h16] <= 32'hXXXXXXXX;
 331         registers['h17] <= 32'hXXXXXXXX;
 332         registers['h18] <= 32'hXXXXXXXX;
 333         registers['h19] <= 32'hXXXXXXXX;
 334         registers['h1A] <= 32'hXXXXXXXX;
 335         registers['h1B] <= 32'hXXXXXXXX;
 336         registers['h1C] <= 32'hXXXXXXXX;
 337         registers['h1D] <= 32'hXXXXXXXX;
 338         registers['h1E] <= 32'hXXXXXXXX;
 339         registers['h1F] <= 32'hXXXXXXXX;
 340     end
 341     endtask
 342
 343     task write_register(input [4:0] register_number, input [31:0] value);
 344     begin
 345         if(register_number != 0)
 346             registers[register_number] <= value;
 347     end
 348     endtask
 349
 350     function [31:0] evaluate_csr_funct3_operation(input [2:0] funct3, input [31:0] previous_value, input [31:0] written_value);
 351     begin
 352         case(funct3)
 353         `funct3_csrrw, `funct3_csrrwi:
 354             evaluate_csr_funct3_operation = written_value;
 355         `funct3_csrrs, `funct3_csrrsi:
 356             evaluate_csr_funct3_operation = written_value | previous_value;
 357         `funct3_csrrc, `funct3_csrrci:
 358             evaluate_csr_funct3_operation = ~written_value & previous_value;
 359         default:
 360             evaluate_csr_funct3_operation = 32'hXXXXXXXX;
 361         endcase
 362     end
 363     endfunction
 364
 365     parameter misa_a = 1'b0;
 366     parameter misa_b = 1'b0;
 367     parameter misa_c = 1'b0;
 368     parameter misa_d = 1'b0;
 369     parameter misa_e = 1'b0;
 370     parameter misa_f = 1'b0;
 371     parameter misa_g = 1'b0;
 372     parameter misa_h = 1'b0;
 373     parameter misa_i = 1'b1;
 374     parameter misa_j = 1'b0;
 375     parameter misa_k = 1'b0;
 376     parameter misa_l = 1'b0;
 377     parameter misa_m = 1'b0;
 378     parameter misa_n = 1'b0;
 379     parameter misa_o = 1'b0;
 380     parameter misa_p = 1'b0;
 381     parameter misa_q = 1'b0;
 382     parameter misa_r = 1'b0;
 383     parameter misa_s = 1'b0;
 384     parameter misa_t = 1'b0;
 385     parameter misa_u = 1'b0;
 386     parameter misa_v = 1'b0;
 387     parameter misa_w = 1'b0;
 388     parameter misa_x = 1'b0;
 389     parameter misa_y = 1'b0;
 390     parameter misa_z = 1'b0;
 391     parameter misa = {
 392         2'b01,
 393         4'b0,
 394         misa_z,
 395         misa_y,
 396         misa_x,
 397         misa_w,
 398         misa_v,
 399         misa_u,
 400         misa_t,
 401         misa_s,
 402         misa_r,
 403         misa_q,
 404         misa_p,
 405         misa_o,
 406         misa_n,
 407         misa_m,
 408         misa_l,
 409         misa_k,
 410         misa_j,
 411         misa_i,
 412         misa_h,
 413         misa_g,
 414         misa_f,
 415         misa_e,
 416         misa_d,
 417         misa_c,
 418         misa_b,
 419         misa_a};
 420
 421     parameter mvendorid = 32'b0;
 422     parameter marchid = 32'b0;
 423     parameter mimpid = 32'b0;
 424     parameter mhartid = 32'b0;
 425
 426     function [31:0] make_mstatus(input mstatus_tsr,
 427         input mstatus_tw,
 428         input mstatus_tvm,
 429         input mstatus_mxr,
 430         input mstatus_sum,
 431         input mstatus_mprv,
 432         input [1:0] mstatus_xs,
 433         input [1:0] mstatus_fs,
 434         input [1:0] mstatus_mpp,
 435         input mstatus_spp,
 436         input mstatus_mpie,
 437         input mstatus_spie,
 438         input mstatus_upie,
 439         input mstatus_mie,
 440         input mstatus_sie,
 441         input mstatus_uie);
 442     begin
 443         make_mstatus = {(mstatus_xs == 2'b11) | (mstatus_fs == 2'b11),
 444             8'b0,
 445             mstatus_tsr,
 446             mstatus_tw,
 447             mstatus_tvm,
 448             mstatus_mxr,
 449             mstatus_sum,
 450             mstatus_mprv,
 451             mstatus_xs,
 452             mstatus_fs,
 453             mstatus_mpp,
 454             2'b0,
 455             mstatus_spp,
 456             mstatus_mpie,
 457             1'b0,
 458             mstatus_spie,
 459             mstatus_upie,
 460             mstatus_mie,
 461             1'b0,
 462             mstatus_sie,
 463             mstatus_uie};
 464     end
 465     endfunction
 466
 467     wire mip_meip = 0; // TODO: implement external interrupts
 468     parameter mip_seip = 0;
 469     parameter mip_ueip = 0;
 470     wire mip_mtip = 0; // TODO: implement timer interrupts
 471     parameter mip_stip = 0;
 472     parameter mip_utip = 0;
 473     parameter mip_msip = 0;
 474     parameter mip_ssip = 0;
 475     parameter mip_usip = 0;
 476
 477     wire csr_op_is_valid;
 478
 479     function `fetch_action get_fetch_action(
 480         input `fetch_output_state fetch_output_state,
 481         input `decode_action decode_action,
 482         input load_store_misaligned,
 483         input memory_interface_rw_address_valid,
 484         input memory_interface_rw_wait,
 485         input branch_taken,
 486         input misaligned_jump_target,
 487         input csr_op_is_valid
 488         );
 489     begin
 490         case(fetch_output_state)
 491         `fetch_output_state_empty:
 492             get_fetch_action = `fetch_action_default;
 493         `fetch_output_state_trap:
 494             get_fetch_action = `fetch_action_ack_trap;
 495         `fetch_output_state_valid: begin
 496             if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 497                 get_fetch_action = `fetch_action_error_trap;
 498             end
 499             else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 500                 get_fetch_action = `fetch_action_noerror_trap;
 501             end
 502             else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
 503                 if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
 504                     get_fetch_action = `fetch_action_error_trap;
 505                 end
 506                 else if(memory_interface_rw_wait) begin
 507                     get_fetch_action = `fetch_action_wait;
 508                 end
 509                 else begin
 510                     get_fetch_action = `fetch_action_default;
 511                 end
 512             end
 513             else if((decode_action & `decode_action_fence_i) != 0) begin
 514                 get_fetch_action = `fetch_action_fence;
 515             end
 516             else if((decode_action & `decode_action_branch) != 0) begin
 517                 if(branch_taken) begin
 518                     if(misaligned_jump_target) begin
 519                         get_fetch_action = `fetch_action_error_trap;
 520                     end
 521                     else begin
 522                         get_fetch_action = `fetch_action_jump;
 523                     end
 524                 end
 525                 else
 526                 begin
 527                     get_fetch_action = `fetch_action_default;
 528                 end
 529             end
 530             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 531                 if(misaligned_jump_target) begin
 532                     get_fetch_action = `fetch_action_error_trap;
 533                 end
 534                 else begin
 535                     get_fetch_action = `fetch_action_jump;
 536                 end
 537             end
 538             else if((decode_action & `decode_action_csr) != 0) begin
 539                 if(csr_op_is_valid)
 540                     get_fetch_action = `fetch_action_default;
 541                 else
 542                     get_fetch_action = `fetch_action_error_trap;
 543             end
 544             else begin
 545                 get_fetch_action = `fetch_action_default;
 546             end
 547         end
 548         default:
 549             get_fetch_action = 32'hXXXXXXXX;
 550         endcase
 551     end
 552     endfunction
 553
 554     assign fetch_action = get_fetch_action(
 555         fetch_output_state,
 556         decode_action,
 557         load_store_misaligned,
 558         memory_interface_rw_address_valid,
 559         memory_interface_rw_wait,
 560         branch_taken,
 561         misaligned_jump_target,
 562         csr_op_is_valid
 563         );
 564
 565     task handle_trap;
 566     begin
 567         mstatus_mpie = mstatus_mie;
 568         mstatus_mie = 0;
 569         mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
 570         if(fetch_action == `fetch_action_ack_trap) begin
 571             mcause = `cause_instruction_access_fault;
 572         end
 573         else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 574             mcause = `cause_illegal_instruction;
 575         end
 576         else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 577             mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
 578         end
 579         else if((decode_action & `decode_action_load) != 0) begin
 580             if(load_store_misaligned)
 581                 mcause = `cause_load_address_misaligned;
 582             else
 583                 mcause = `cause_load_access_fault;
 584         end
 585         else if((decode_action & `decode_action_store) != 0) begin
 586             if(load_store_misaligned)
 587                 mcause = `cause_store_amo_address_misaligned;
 588             else
 589                 mcause = `cause_store_amo_access_fault;
 590         end
 591         else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
 592             mcause = `cause_instruction_address_misaligned;
 593         end
 594         else begin
 595             mcause = `cause_illegal_instruction;
 596         end
 597     end
 598     endtask
 599
 600     wire [11:0] csr_number = decoder_immediate;
 601     wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
 602     wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
 603     wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
 604
 605     function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
 606     begin
 607         case(csr_number)
 608         `csr_ustatus,
 609         `csr_fflags,
 610         `csr_frm,
 611         `csr_fcsr,
 612         `csr_uie,
 613         `csr_utvec,
 614         `csr_uscratch,
 615         `csr_uepc,
 616         `csr_ucause,
 617         `csr_utval,
 618         `csr_uip,
 619         `csr_sstatus,
 620         `csr_sedeleg,
 621         `csr_sideleg,
 622         `csr_sie,
 623         `csr_stvec,
 624         `csr_scounteren,
 625         `csr_sscratch,
 626         `csr_sepc,
 627         `csr_scause,
 628         `csr_stval,
 629         `csr_sip,
 630         `csr_satp,
 631         `csr_medeleg,
 632         `csr_mideleg,
 633         `csr_dcsr,
 634         `csr_dpc,
 635         `csr_dscratch:
 636             get_csr_op_is_valid = 0;
 637         `csr_cycle,
 638         `csr_time,
 639         `csr_instret,
 640         `csr_cycleh,
 641         `csr_timeh,
 642         `csr_instreth,
 643         `csr_mvendorid,
 644         `csr_marchid,
 645         `csr_mimpid,
 646         `csr_mhartid:
 647             get_csr_op_is_valid = ~csr_writes;
 648         `csr_misa,
 649         `csr_mstatus,
 650         `csr_mie,
 651         `csr_mtvec,
 652         `csr_mscratch,
 653         `csr_mepc,
 654         `csr_mcause,
 655         `csr_mip:
 656             get_csr_op_is_valid = 1;
 657         `csr_mcounteren,
 658         `csr_mtval,
 659         `csr_mcycle,
 660         `csr_minstret,
 661         `csr_mcycleh,
 662         `csr_minstreth:
 663             // TODO: CSRs not implemented yet
 664             get_csr_op_is_valid = 0;
 665         endcase
 666     end
 667     endfunction
 668
 669     assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
 670
 671     wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
 672     wire [63:0] time_counter = 0; // TODO: implement time_counter
 673     wire [63:0] instret_counter = 0; // TODO: implement instret_counter
 674
 675     always @(posedge clk) begin:main_block
 676         if(reset) begin
 677             reset_to_initial();
 678             disable main_block;
 679         end
 680         case(fetch_output_state)
 681         `fetch_output_state_empty: begin
 682         end
 683         `fetch_output_state_trap: begin
 684             handle_trap();
 685         end
 686         `fetch_output_state_valid: begin:valid
 687             if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
 688                 handle_trap();
 689             end
 690             else if((decode_action & `decode_action_load) != 0) begin
 691                 if(~memory_interface_rw_wait)
 692                     write_register(decoder_rd, loaded_value);
 693             end
 694             else if((decode_action & `decode_action_op_op_imm) != 0) begin
 695                 write_register(decoder_rd, alu_result);
 696             end
 697             else if((decode_action & `decode_action_lui_auipc) != 0) begin
 698                 write_register(decoder_rd, lui_auipc_result);
 699             end
 700             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 701                 write_register(decoder_rd, fetch_output_pc + 4);
 702             end
 703             else if((decode_action & `decode_action_csr) != 0) begin:csr
 704                 reg [31:0] csr_output_value;
 705                 reg [31:0] csr_written_value;
 706                 csr_output_value = 32'hXXXXXXXX;
 707                 csr_written_value = 32'hXXXXXXXX;
 708                 case(csr_number)
 709                 `csr_cycle: begin
 710                     csr_output_value = cycle_counter[31:0];
 711                 end
 712                 `csr_time: begin
 713                     csr_output_value = time_counter[31:0];
 714                 end
 715                 `csr_instret: begin
 716                     csr_output_value = instret_counter[31:0];
 717                 end
 718                 `csr_cycleh: begin
 719                     csr_output_value = cycle_counter[63:32];
 720                 end
 721                 `csr_timeh: begin
 722                     csr_output_value = time_counter[63:32];
 723                 end
 724                 `csr_instreth: begin
 725                     csr_output_value = instret_counter[63:32];
 726                 end
 727                 `csr_mvendorid: begin
 728                     csr_output_value = mvendorid;
 729                 end
 730                 `csr_marchid: begin
 731                     csr_output_value = marchid;
 732                 end
 733                 `csr_mimpid: begin
 734                     csr_output_value = mimpid;
 735                 end
 736                 `csr_mhartid: begin
 737                     csr_output_value = mhartid;
 738                 end
 739                 `csr_misa: begin
 740                     csr_output_value = misa;
 741                 end
 742                 `csr_mstatus: begin
 743                     csr_output_value = make_mstatus(mstatus_tsr,
 744                                                     mstatus_tw,
 745                                                     mstatus_tvm,
 746                                                     mstatus_mxr,
 747                                                     mstatus_sum,
 748                                                     mstatus_mprv,
 749                                                     mstatus_xs,
 750                                                     mstatus_fs,
 751                                                     mstatus_mpp,
 752                                                     mstatus_spp,
 753                                                     mstatus_mpie,
 754                                                     mstatus_spie,
 755                                                     mstatus_upie,
 756                                                     mstatus_mie,
 757                                                     mstatus_sie,
 758                                                     mstatus_uie);
 759                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 760                     if(csr_writes) begin
 761                         mstatus_mpie = csr_written_value[7];
 762                         mstatus_mie = csr_written_value[3];
 763                     end
 764                 end
 765                 `csr_mie: begin
 766                     csr_output_value = 0;
 767                     csr_output_value[11] = mie_meie;
 768                     csr_output_value[9] = mie_seie;
 769                     csr_output_value[8] = mie_ueie;
 770                     csr_output_value[7] = mie_mtie;
 771                     csr_output_value[5] = mie_stie;
 772                     csr_output_value[4] = mie_utie;
 773                     csr_output_value[3] = mie_msie;
 774                     csr_output_value[1] = mie_ssie;
 775                     csr_output_value[0] = mie_usie;
 776                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 777                     if(csr_writes) begin
 778                         mie_meie = csr_written_value[11];
 779                         mie_mtie = csr_written_value[7];
 780                         mie_msie = csr_written_value[3];
 781                     end
 782                 end
 783                 `csr_mtvec: begin
 784                     csr_output_value = mtvec;
 785                 end
 786                 `csr_mscratch: begin
 787                     csr_output_value = mscratch;
 788                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 789                     if(csr_writes)
 790                         mscratch = csr_written_value;
 791                 end
 792                 `csr_mepc: begin
 793                     csr_output_value = mepc;
 794                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 795                     if(csr_writes)
 796                         mepc = csr_written_value;
 797                 end
 798                 `csr_mcause: begin
 799                     csr_output_value = mcause;
 800                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 801                     if(csr_writes)
 802                         mcause = csr_written_value;
 803                 end
 804                 `csr_mip: begin
 805                     csr_output_value = 0;
 806                     csr_output_value[11] = mip_meip;
 807                     csr_output_value[9] = mip_seip;
 808                     csr_output_value[8] = mip_ueip;
 809                     csr_output_value[7] = mip_mtip;
 810                     csr_output_value[5] = mip_stip;
 811                     csr_output_value[4] = mip_utip;
 812                     csr_output_value[3] = mip_msip;
 813                     csr_output_value[1] = mip_ssip;
 814                     csr_output_value[0] = mip_usip;
 815                 end
 816                 endcase
 817                 if(csr_reads)
 818                     write_register(decoder_rd, csr_output_value);
 819             end
 820             else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin
 821                 // do nothing
 822             end
 823         end
 824         endcase
 825     end
 826
 827 endmodule
 828 """
 829