cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 from migen import *
  30 from migen.fhdl import verilog
  31
  32 from riscvdefs import *
  33 from cpudefs import *
  34
  35 class CPU(Module):
  36     """
  37     """
  38
  39     def __init__(self):
  40         #self.clk = ClockSignal()
  41         #self.reset = ResetSignal()
  42         self.tty_write = Signal()
  43         self.tty_write_data = Signal(8)
  44         self.tty_write_busy = Signal()
  45         self.switch_2 = Signal()
  46         self.switch_3 = Signal()
  47         self.led_1 = Signal()
  48         self.led_3 = Signal()
  49
  50         ram_size = Constant(0x8000)
  51         ram_start = Constant(0x10000, 32)
  52         reset_vector = Signal(32)
  53         mtvec = Signal(32)
  54
  55         reset_vector.eq(ram_start)
  56         mtvec.eq(ram_start + 0x40)
  57
  58         l = []
  59         for i in range(31):
  60             l.append(Signal(32, name="register%d" % i))
  61         registers = Array(l)
  62
  63         #self.sync += self.registers[0].eq(0)
  64         #self.sync += self.registers[1].eq(0)
  65
  66         memory_interface_fetch_address = Signal(32) # XXX [2:]
  67         memory_interface_fetch_data = Signal(32)
  68         memory_interface_fetch_valid = Signal()
  69         memory_interface_rw_address= Signal(32) # XXX [2:]
  70         memory_interface_rw_byte_mask = Signal(4)
  71         memory_interface_rw_read_not_write = Signal()
  72         memory_interface_rw_active = Signal()
  73         memory_interface_rw_data_in = Signal(32)
  74         memory_interface_rw_data_out = Signal(32)
  75         memory_interface_rw_address_valid = Signal()
  76         memory_interface_rw_wait = Signal()
  77
  78         mi = Instance("cpu_memory_interface", name="memory_instance",
  79                     p_ram_size = ram_size,
  80                     p_ram_start = ram_start,
  81                     i_clk=ClockSignal(),
  82                     i_rst=ResetSignal(),
  83                     i_fetch_address = memory_interface_fetch_address,
  84                     o_fetch_data = memory_interface_fetch_data,
  85                     o_fetch_valid = memory_interface_fetch_valid,
  86                     i_rw_address = memory_interface_rw_address,
  87                     i_rw_byte_mask = memory_interface_rw_byte_mask,
  88                     i_rw_read_not_write = memory_interface_rw_read_not_write,
  89                     i_rw_active = memory_interface_rw_active,
  90                     i_rw_data_in = memory_interface_rw_data_in,
  91                     o_rw_data_out = memory_interface_rw_data_out,
  92                     o_rw_address_valid = memory_interface_rw_address_valid,
  93                     o_rw_wait = memory_interface_rw_wait,
  94                     o_tty_write = self.tty_write,
  95                     o_tty_write_data = self.tty_write_data,
  96                     i_tty_write_busy = self.tty_write_busy,
  97                     i_switch_2 = self.switch_2,
  98                     i_switch_3 = self.switch_3,
  99                     o_led_1 = self.led_1,
 100                     o_led_3 = self.led_3
 101                   )
 102         self.specials += mi
 103
 104         fetch_act = Signal(fetch_action)
 105         fetch_target_pc = Signal(32)
 106         fetch_output_pc = Signal(32)
 107         fetch_output_instruction = Signal(32)
 108         fetch_output_st = Signal(fetch_output_state)
 109
 110         fs = Instance("CPUFetchStage", name="fetch_stage",
 111             i_clk=ClockSignal(),
 112             i_rst=ResetSignal(),
 113             o_memory_interface_fetch_address = memory_interface_fetch_address,
 114             i_memory_interface_fetch_data = memory_interface_fetch_data,
 115             i_memory_interface_fetch_valid = memory_interface_fetch_valid,
 116             i_fetch_action = fetch_act,
 117             i_target_pc = fetch_target_pc,
 118             o_output_pc = fetch_output_pc,
 119             o_output_instruction = fetch_output_instruction,
 120             o_output_state = fetch_output_st,
 121             i_reset_vector = reset_vector,
 122             i_mtvec = mtvec,
 123         )
 124         self.specials += fs
 125
 126         decoder_funct7 = Signal(7)
 127         decoder_funct3 = Signal(3)
 128         decoder_rd = Signal(5)
 129         decoder_rs1 = Signal(5)
 130         decoder_rs2 = Signal(5)
 131         decoder_immediate = Signal(32)
 132         decoder_opcode = Signal(7)
 133         decode_act = Signal(decode_action)
 134
 135         cd = Instance("CPUDecoder", name="decoder",
 136             i_instruction = fetch_output_instruction,
 137             o_funct7 = decoder_funct7,
 138             o_funct3 = decoder_funct3,
 139             o_rd = decoder_rd,
 140             o_rs1 = decoder_rs1,
 141             o_rs2 = decoder_rs2,
 142             o_immediate = decoder_immediate,
 143             o_opcode = decoder_opcode,
 144             o_decode_action = decode_act
 145         )
 146         self.specials += cd
 147
 148         register_rs1 = Signal(32)
 149         register_rs2 = Signal(32)
 150         self.comb += If(decoder_rs1 == 0,
 151                         register_rs1.eq(0)
 152                      ).Else(
 153                         register_rs1.eq(registers[decoder_rs1-1]))
 154         self.comb += If(decoder_rs2 == 0,
 155                         register_rs2.eq(0)
 156                      ).Else(
 157                         register_rs2.eq(registers[decoder_rs2-1]))
 158
 159         load_store_address = Signal(32)
 160         load_store_address_low_2 = Signal(2)
 161
 162         self.comb += load_store_address.eq(decoder_immediate + register_rs1)
 163         self.comb += load_store_address_low_2.eq(
 164                             decoder_immediate[:2] + register_rs1[:2])
 165
 166
 167 if __name__ == "__main__":
 168     example = CPU()
 169     print(verilog.convert(example,
 170          {
 171            example.tty_write,
 172            example.tty_write_data,
 173            example.tty_write_busy,
 174            example.switch_2,
 175            example.switch_3,
 176            example.led_1,
 177            example.led_3,
 178            }))
 179
 180 """
 181
 182     function get_load_store_misaligned(
 183         input [2:0] funct3,
 184         input [1:0] load_store_address_low_2
 185         );
 186     begin
 187         case(funct3[1:0])
 188         `funct3_sb:
 189             get_load_store_misaligned = 0;
 190         `funct3_sh:
 191             get_load_store_misaligned = load_store_address_low_2[0] != 0;
 192         `funct3_sw:
 193             get_load_store_misaligned = load_store_address_low_2[1:0] != 0;
 194         default:
 195             get_load_store_misaligned = 1'bX;
 196         endcase
 197     end
 198     endfunction
 199
 200     wire load_store_misaligned = get_load_store_misaligned(decoder_funct3, load_store_address_low_2);
 201
 202     assign memory_interface_rw_address = load_store_address[31:2];
 203
 204     wire [3:0] unshifted_load_store_byte_mask = {decoder_funct3[1] ? 2'b11 : 2'b00, (decoder_funct3[1] | decoder_funct3[0]) ? 1'b1 : 1'b0, 1'b1};
 205
 206     assign memory_interface_rw_byte_mask = unshifted_load_store_byte_mask << load_store_address_low_2;
 207
 208     assign memory_interface_rw_data_in[31:24] = load_store_address_low_2[1]
 209                                                 ? (load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8])
 210                                                 : (load_store_address_low_2[0] ? register_rs2[23:16] : register_rs2[31:24]);
 211     assign memory_interface_rw_data_in[23:16] = load_store_address_low_2[1] ? register_rs2[7:0] : register_rs2[23:16];
 212     assign memory_interface_rw_data_in[15:8] = load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8];
 213     assign memory_interface_rw_data_in[7:0] = register_rs2[7:0];
 214
 215     wire [31:0] unmasked_loaded_value;
 216
 217     assign unmasked_loaded_value[7:0] = load_store_address_low_2[1]
 218                                         ? (load_store_address_low_2[0] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[23:16])
 219                                         : (load_store_address_low_2[0] ? memory_interface_rw_data_out[15:8] : memory_interface_rw_data_out[7:0]);
 220     assign unmasked_loaded_value[15:8] = load_store_address_low_2[1] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[15:8];
 221     assign unmasked_loaded_value[31:16] = memory_interface_rw_data_out[31:16];
 222
 223     wire [31:0] loaded_value;
 224
 225     assign loaded_value[7:0] = unmasked_loaded_value[7:0];
 226     assign loaded_value[15:8] = decoder_funct3[1:0] == 0 ? ({8{~decoder_funct3[2] & unmasked_loaded_value[7]}}) : unmasked_loaded_value[15:8];
 227     assign loaded_value[31:16] = decoder_funct3[1] == 0 ? ({16{~decoder_funct3[2] & (decoder_funct3[0] ? unmasked_loaded_value[15] : unmasked_loaded_value[7])}}) : unmasked_loaded_value[31:16];
 228
 229     assign memory_interface_rw_active = ~reset
 230                                         & (fetch_output_state == `fetch_output_state_valid)
 231                                         & ~load_store_misaligned
 232                                         & ((decode_action & (`decode_action_load | `decode_action_store)) != 0);
 233
 234     assign memory_interface_rw_read_not_write = ~decoder_opcode[5];
 235
 236     wire [31:0] alu_a = register_rs1;
 237     wire [31:0] alu_b = decoder_opcode[5] ? register_rs2 : decoder_immediate;
 238     wire [31:0] alu_result;
 239
 240     cpu_alu alu(
 241         .funct7(decoder_funct7),
 242         .funct3(decoder_funct3),
 243         .opcode(decoder_opcode),
 244         .a(alu_a),
 245         .b(alu_b),
 246         .result(alu_result)
 247         );
 248
 249     wire [31:0] lui_auipc_result = decoder_opcode[5] ? decoder_immediate : decoder_immediate + fetch_output_pc;
 250
 251     assign fetch_target_pc[31:1] = ((decoder_opcode != `opcode_jalr ? fetch_output_pc[31:1] : register_rs1[31:1]) + decoder_immediate[31:1]);
 252     assign fetch_target_pc[0] = 0;
 253
 254     wire misaligned_jump_target = fetch_target_pc[1];
 255
 256     wire [31:0] branch_arg_a = {register_rs1[31] ^ ~decoder_funct3[1], register_rs1[30:0]};
 257     wire [31:0] branch_arg_b = {register_rs2[31] ^ ~decoder_funct3[1], register_rs2[30:0]};
 258
 259     wire branch_taken = decoder_funct3[0] ^ (decoder_funct3[2] ? branch_arg_a < branch_arg_b : branch_arg_a == branch_arg_b);
 260
 261     reg [31:0] mcause = 0;
 262     reg [31:0] mepc = 32'hXXXXXXXX;
 263     reg [31:0] mscratch = 32'hXXXXXXXX;
 264
 265     reg mstatus_mpie = 1'bX;
 266     reg mstatus_mie = 0;
 267     parameter mstatus_mprv = 0;
 268     parameter mstatus_tsr = 0;
 269     parameter mstatus_tw = 0;
 270     parameter mstatus_tvm = 0;
 271     parameter mstatus_mxr = 0;
 272     parameter mstatus_sum = 0;
 273     parameter mstatus_xs = 0;
 274     parameter mstatus_fs = 0;
 275     parameter mstatus_mpp = 2'b11;
 276     parameter mstatus_spp = 0;
 277     parameter mstatus_spie = 0;
 278     parameter mstatus_upie = 0;
 279     parameter mstatus_sie = 0;
 280     parameter mstatus_uie = 0;
 281
 282     reg mie_meie = 1'bX;
 283     reg mie_mtie = 1'bX;
 284     reg mie_msie = 1'bX;
 285     parameter mie_seie = 0;
 286     parameter mie_ueie = 0;
 287     parameter mie_stie = 0;
 288     parameter mie_utie = 0;
 289     parameter mie_ssie = 0;
 290     parameter mie_usie = 0;
 291
 292     task reset_to_initial;
 293     begin
 294         mcause = 0;
 295         mepc = 32'hXXXXXXXX;
 296         mscratch = 32'hXXXXXXXX;
 297         mstatus_mie = 0;
 298         mstatus_mpie = 1'bX;
 299         mie_meie = 1'bX;
 300         mie_mtie = 1'bX;
 301         mie_msie = 1'bX;
 302         registers['h01] <= 32'hXXXXXXXX;
 303         registers['h02] <= 32'hXXXXXXXX;
 304         registers['h03] <= 32'hXXXXXXXX;
 305         registers['h04] <= 32'hXXXXXXXX;
 306         registers['h05] <= 32'hXXXXXXXX;
 307         registers['h06] <= 32'hXXXXXXXX;
 308         registers['h07] <= 32'hXXXXXXXX;
 309         registers['h08] <= 32'hXXXXXXXX;
 310         registers['h09] <= 32'hXXXXXXXX;
 311         registers['h0A] <= 32'hXXXXXXXX;
 312         registers['h0B] <= 32'hXXXXXXXX;
 313         registers['h0C] <= 32'hXXXXXXXX;
 314         registers['h0D] <= 32'hXXXXXXXX;
 315         registers['h0E] <= 32'hXXXXXXXX;
 316         registers['h0F] <= 32'hXXXXXXXX;
 317         registers['h10] <= 32'hXXXXXXXX;
 318         registers['h11] <= 32'hXXXXXXXX;
 319         registers['h12] <= 32'hXXXXXXXX;
 320         registers['h13] <= 32'hXXXXXXXX;
 321         registers['h14] <= 32'hXXXXXXXX;
 322         registers['h15] <= 32'hXXXXXXXX;
 323         registers['h16] <= 32'hXXXXXXXX;
 324         registers['h17] <= 32'hXXXXXXXX;
 325         registers['h18] <= 32'hXXXXXXXX;
 326         registers['h19] <= 32'hXXXXXXXX;
 327         registers['h1A] <= 32'hXXXXXXXX;
 328         registers['h1B] <= 32'hXXXXXXXX;
 329         registers['h1C] <= 32'hXXXXXXXX;
 330         registers['h1D] <= 32'hXXXXXXXX;
 331         registers['h1E] <= 32'hXXXXXXXX;
 332         registers['h1F] <= 32'hXXXXXXXX;
 333     end
 334     endtask
 335
 336     task write_register(input [4:0] register_number, input [31:0] value);
 337     begin
 338         if(register_number != 0)
 339             registers[register_number] <= value;
 340     end
 341     endtask
 342
 343     function [31:0] evaluate_csr_funct3_operation(input [2:0] funct3, input [31:0] previous_value, input [31:0] written_value);
 344     begin
 345         case(funct3)
 346         `funct3_csrrw, `funct3_csrrwi:
 347             evaluate_csr_funct3_operation = written_value;
 348         `funct3_csrrs, `funct3_csrrsi:
 349             evaluate_csr_funct3_operation = written_value | previous_value;
 350         `funct3_csrrc, `funct3_csrrci:
 351             evaluate_csr_funct3_operation = ~written_value & previous_value;
 352         default:
 353             evaluate_csr_funct3_operation = 32'hXXXXXXXX;
 354         endcase
 355     end
 356     endfunction
 357
 358     parameter misa_a = 1'b0;
 359     parameter misa_b = 1'b0;
 360     parameter misa_c = 1'b0;
 361     parameter misa_d = 1'b0;
 362     parameter misa_e = 1'b0;
 363     parameter misa_f = 1'b0;
 364     parameter misa_g = 1'b0;
 365     parameter misa_h = 1'b0;
 366     parameter misa_i = 1'b1;
 367     parameter misa_j = 1'b0;
 368     parameter misa_k = 1'b0;
 369     parameter misa_l = 1'b0;
 370     parameter misa_m = 1'b0;
 371     parameter misa_n = 1'b0;
 372     parameter misa_o = 1'b0;
 373     parameter misa_p = 1'b0;
 374     parameter misa_q = 1'b0;
 375     parameter misa_r = 1'b0;
 376     parameter misa_s = 1'b0;
 377     parameter misa_t = 1'b0;
 378     parameter misa_u = 1'b0;
 379     parameter misa_v = 1'b0;
 380     parameter misa_w = 1'b0;
 381     parameter misa_x = 1'b0;
 382     parameter misa_y = 1'b0;
 383     parameter misa_z = 1'b0;
 384     parameter misa = {
 385         2'b01,
 386         4'b0,
 387         misa_z,
 388         misa_y,
 389         misa_x,
 390         misa_w,
 391         misa_v,
 392         misa_u,
 393         misa_t,
 394         misa_s,
 395         misa_r,
 396         misa_q,
 397         misa_p,
 398         misa_o,
 399         misa_n,
 400         misa_m,
 401         misa_l,
 402         misa_k,
 403         misa_j,
 404         misa_i,
 405         misa_h,
 406         misa_g,
 407         misa_f,
 408         misa_e,
 409         misa_d,
 410         misa_c,
 411         misa_b,
 412         misa_a};
 413
 414     parameter mvendorid = 32'b0;
 415     parameter marchid = 32'b0;
 416     parameter mimpid = 32'b0;
 417     parameter mhartid = 32'b0;
 418
 419     function [31:0] make_mstatus(input mstatus_tsr,
 420         input mstatus_tw,
 421         input mstatus_tvm,
 422         input mstatus_mxr,
 423         input mstatus_sum,
 424         input mstatus_mprv,
 425         input [1:0] mstatus_xs,
 426         input [1:0] mstatus_fs,
 427         input [1:0] mstatus_mpp,
 428         input mstatus_spp,
 429         input mstatus_mpie,
 430         input mstatus_spie,
 431         input mstatus_upie,
 432         input mstatus_mie,
 433         input mstatus_sie,
 434         input mstatus_uie);
 435     begin
 436         make_mstatus = {(mstatus_xs == 2'b11) | (mstatus_fs == 2'b11),
 437             8'b0,
 438             mstatus_tsr,
 439             mstatus_tw,
 440             mstatus_tvm,
 441             mstatus_mxr,
 442             mstatus_sum,
 443             mstatus_mprv,
 444             mstatus_xs,
 445             mstatus_fs,
 446             mstatus_mpp,
 447             2'b0,
 448             mstatus_spp,
 449             mstatus_mpie,
 450             1'b0,
 451             mstatus_spie,
 452             mstatus_upie,
 453             mstatus_mie,
 454             1'b0,
 455             mstatus_sie,
 456             mstatus_uie};
 457     end
 458     endfunction
 459
 460     wire mip_meip = 0; // TODO: implement external interrupts
 461     parameter mip_seip = 0;
 462     parameter mip_ueip = 0;
 463     wire mip_mtip = 0; // TODO: implement timer interrupts
 464     parameter mip_stip = 0;
 465     parameter mip_utip = 0;
 466     parameter mip_msip = 0;
 467     parameter mip_ssip = 0;
 468     parameter mip_usip = 0;
 469
 470     wire csr_op_is_valid;
 471
 472     function `fetch_action get_fetch_action(
 473         input `fetch_output_state fetch_output_state,
 474         input `decode_action decode_action,
 475         input load_store_misaligned,
 476         input memory_interface_rw_address_valid,
 477         input memory_interface_rw_wait,
 478         input branch_taken,
 479         input misaligned_jump_target,
 480         input csr_op_is_valid
 481         );
 482     begin
 483         case(fetch_output_state)
 484         `fetch_output_state_empty:
 485             get_fetch_action = `fetch_action_default;
 486         `fetch_output_state_trap:
 487             get_fetch_action = `fetch_action_ack_trap;
 488         `fetch_output_state_valid: begin
 489             if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 490                 get_fetch_action = `fetch_action_error_trap;
 491             end
 492             else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 493                 get_fetch_action = `fetch_action_noerror_trap;
 494             end
 495             else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
 496                 if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
 497                     get_fetch_action = `fetch_action_error_trap;
 498                 end
 499                 else if(memory_interface_rw_wait) begin
 500                     get_fetch_action = `fetch_action_wait;
 501                 end
 502                 else begin
 503                     get_fetch_action = `fetch_action_default;
 504                 end
 505             end
 506             else if((decode_action & `decode_action_fence_i) != 0) begin
 507                 get_fetch_action = `fetch_action_fence;
 508             end
 509             else if((decode_action & `decode_action_branch) != 0) begin
 510                 if(branch_taken) begin
 511                     if(misaligned_jump_target) begin
 512                         get_fetch_action = `fetch_action_error_trap;
 513                     end
 514                     else begin
 515                         get_fetch_action = `fetch_action_jump;
 516                     end
 517                 end
 518                 else
 519                 begin
 520                     get_fetch_action = `fetch_action_default;
 521                 end
 522             end
 523             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 524                 if(misaligned_jump_target) begin
 525                     get_fetch_action = `fetch_action_error_trap;
 526                 end
 527                 else begin
 528                     get_fetch_action = `fetch_action_jump;
 529                 end
 530             end
 531             else if((decode_action & `decode_action_csr) != 0) begin
 532                 if(csr_op_is_valid)
 533                     get_fetch_action = `fetch_action_default;
 534                 else
 535                     get_fetch_action = `fetch_action_error_trap;
 536             end
 537             else begin
 538                 get_fetch_action = `fetch_action_default;
 539             end
 540         end
 541         default:
 542             get_fetch_action = 32'hXXXXXXXX;
 543         endcase
 544     end
 545     endfunction
 546
 547     assign fetch_action = get_fetch_action(
 548         fetch_output_state,
 549         decode_action,
 550         load_store_misaligned,
 551         memory_interface_rw_address_valid,
 552         memory_interface_rw_wait,
 553         branch_taken,
 554         misaligned_jump_target,
 555         csr_op_is_valid
 556         );
 557
 558     task handle_trap;
 559     begin
 560         mstatus_mpie = mstatus_mie;
 561         mstatus_mie = 0;
 562         mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
 563         if(fetch_action == `fetch_action_ack_trap) begin
 564             mcause = `cause_instruction_access_fault;
 565         end
 566         else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 567             mcause = `cause_illegal_instruction;
 568         end
 569         else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 570             mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
 571         end
 572         else if((decode_action & `decode_action_load) != 0) begin
 573             if(load_store_misaligned)
 574                 mcause = `cause_load_address_misaligned;
 575             else
 576                 mcause = `cause_load_access_fault;
 577         end
 578         else if((decode_action & `decode_action_store) != 0) begin
 579             if(load_store_misaligned)
 580                 mcause = `cause_store_amo_address_misaligned;
 581             else
 582                 mcause = `cause_store_amo_access_fault;
 583         end
 584         else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
 585             mcause = `cause_instruction_address_misaligned;
 586         end
 587         else begin
 588             mcause = `cause_illegal_instruction;
 589         end
 590     end
 591     endtask
 592
 593     wire [11:0] csr_number = decoder_immediate;
 594     wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
 595     wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
 596     wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
 597
 598     function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
 599     begin
 600         case(csr_number)
 601         `csr_ustatus,
 602         `csr_fflags,
 603         `csr_frm,
 604         `csr_fcsr,
 605         `csr_uie,
 606         `csr_utvec,
 607         `csr_uscratch,
 608         `csr_uepc,
 609         `csr_ucause,
 610         `csr_utval,
 611         `csr_uip,
 612         `csr_sstatus,
 613         `csr_sedeleg,
 614         `csr_sideleg,
 615         `csr_sie,
 616         `csr_stvec,
 617         `csr_scounteren,
 618         `csr_sscratch,
 619         `csr_sepc,
 620         `csr_scause,
 621         `csr_stval,
 622         `csr_sip,
 623         `csr_satp,
 624         `csr_medeleg,
 625         `csr_mideleg,
 626         `csr_dcsr,
 627         `csr_dpc,
 628         `csr_dscratch:
 629             get_csr_op_is_valid = 0;
 630         `csr_cycle,
 631         `csr_time,
 632         `csr_instret,
 633         `csr_cycleh,
 634         `csr_timeh,
 635         `csr_instreth,
 636         `csr_mvendorid,
 637         `csr_marchid,
 638         `csr_mimpid,
 639         `csr_mhartid:
 640             get_csr_op_is_valid = ~csr_writes;
 641         `csr_misa,
 642         `csr_mstatus,
 643         `csr_mie,
 644         `csr_mtvec,
 645         `csr_mscratch,
 646         `csr_mepc,
 647         `csr_mcause,
 648         `csr_mip:
 649             get_csr_op_is_valid = 1;
 650         `csr_mcounteren,
 651         `csr_mtval,
 652         `csr_mcycle,
 653         `csr_minstret,
 654         `csr_mcycleh,
 655         `csr_minstreth:
 656             // TODO: CSRs not implemented yet
 657             get_csr_op_is_valid = 0;
 658         endcase
 659     end
 660     endfunction
 661
 662     assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
 663
 664     wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
 665     wire [63:0] time_counter = 0; // TODO: implement time_counter
 666     wire [63:0] instret_counter = 0; // TODO: implement instret_counter
 667
 668     always @(posedge clk) begin:main_block
 669         if(reset) begin
 670             reset_to_initial();
 671             disable main_block;
 672         end
 673         case(fetch_output_state)
 674         `fetch_output_state_empty: begin
 675         end
 676         `fetch_output_state_trap: begin
 677             handle_trap();
 678         end
 679         `fetch_output_state_valid: begin:valid
 680             if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
 681                 handle_trap();
 682             end
 683             else if((decode_action & `decode_action_load) != 0) begin
 684                 if(~memory_interface_rw_wait)
 685                     write_register(decoder_rd, loaded_value);
 686             end
 687             else if((decode_action & `decode_action_op_op_imm) != 0) begin
 688                 write_register(decoder_rd, alu_result);
 689             end
 690             else if((decode_action & `decode_action_lui_auipc) != 0) begin
 691                 write_register(decoder_rd, lui_auipc_result);
 692             end
 693             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 694                 write_register(decoder_rd, fetch_output_pc + 4);
 695             end
 696             else if((decode_action & `decode_action_csr) != 0) begin:csr
 697                 reg [31:0] csr_output_value;
 698                 reg [31:0] csr_written_value;
 699                 csr_output_value = 32'hXXXXXXXX;
 700                 csr_written_value = 32'hXXXXXXXX;
 701                 case(csr_number)
 702                 `csr_cycle: begin
 703                     csr_output_value = cycle_counter[31:0];
 704                 end
 705                 `csr_time: begin
 706                     csr_output_value = time_counter[31:0];
 707                 end
 708                 `csr_instret: begin
 709                     csr_output_value = instret_counter[31:0];
 710                 end
 711                 `csr_cycleh: begin
 712                     csr_output_value = cycle_counter[63:32];
 713                 end
 714                 `csr_timeh: begin
 715                     csr_output_value = time_counter[63:32];
 716                 end
 717                 `csr_instreth: begin
 718                     csr_output_value = instret_counter[63:32];
 719                 end
 720                 `csr_mvendorid: begin
 721                     csr_output_value = mvendorid;
 722                 end
 723                 `csr_marchid: begin
 724                     csr_output_value = marchid;
 725                 end
 726                 `csr_mimpid: begin
 727                     csr_output_value = mimpid;
 728                 end
 729                 `csr_mhartid: begin
 730                     csr_output_value = mhartid;
 731                 end
 732                 `csr_misa: begin
 733                     csr_output_value = misa;
 734                 end
 735                 `csr_mstatus: begin
 736                     csr_output_value = make_mstatus(mstatus_tsr,
 737                                                     mstatus_tw,
 738                                                     mstatus_tvm,
 739                                                     mstatus_mxr,
 740                                                     mstatus_sum,
 741                                                     mstatus_mprv,
 742                                                     mstatus_xs,
 743                                                     mstatus_fs,
 744                                                     mstatus_mpp,
 745                                                     mstatus_spp,
 746                                                     mstatus_mpie,
 747                                                     mstatus_spie,
 748                                                     mstatus_upie,
 749                                                     mstatus_mie,
 750                                                     mstatus_sie,
 751                                                     mstatus_uie);
 752                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 753                     if(csr_writes) begin
 754                         mstatus_mpie = csr_written_value[7];
 755                         mstatus_mie = csr_written_value[3];
 756                     end
 757                 end
 758                 `csr_mie: begin
 759                     csr_output_value = 0;
 760                     csr_output_value[11] = mie_meie;
 761                     csr_output_value[9] = mie_seie;
 762                     csr_output_value[8] = mie_ueie;
 763                     csr_output_value[7] = mie_mtie;
 764                     csr_output_value[5] = mie_stie;
 765                     csr_output_value[4] = mie_utie;
 766                     csr_output_value[3] = mie_msie;
 767                     csr_output_value[1] = mie_ssie;
 768                     csr_output_value[0] = mie_usie;
 769                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 770                     if(csr_writes) begin
 771                         mie_meie = csr_written_value[11];
 772                         mie_mtie = csr_written_value[7];
 773                         mie_msie = csr_written_value[3];
 774                     end
 775                 end
 776                 `csr_mtvec: begin
 777                     csr_output_value = mtvec;
 778                 end
 779                 `csr_mscratch: begin
 780                     csr_output_value = mscratch;
 781                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 782                     if(csr_writes)
 783                         mscratch = csr_written_value;
 784                 end
 785                 `csr_mepc: begin
 786                     csr_output_value = mepc;
 787                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 788                     if(csr_writes)
 789                         mepc = csr_written_value;
 790                 end
 791                 `csr_mcause: begin
 792                     csr_output_value = mcause;
 793                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 794                     if(csr_writes)
 795                         mcause = csr_written_value;
 796                 end
 797                 `csr_mip: begin
 798                     csr_output_value = 0;
 799                     csr_output_value[11] = mip_meip;
 800                     csr_output_value[9] = mip_seip;
 801                     csr_output_value[8] = mip_ueip;
 802                     csr_output_value[7] = mip_mtip;
 803                     csr_output_value[5] = mip_stip;
 804                     csr_output_value[4] = mip_utip;
 805                     csr_output_value[3] = mip_msip;
 806                     csr_output_value[1] = mip_ssip;
 807                     csr_output_value[0] = mip_usip;
 808                 end
 809                 endcase
 810                 if(csr_reads)
 811                     write_register(decoder_rd, csr_output_value);
 812             end
 813             else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin
 814                 // do nothing
 815             end
 816         end
 817         endcase
 818     end
 819
 820 endmodule
 821 """
 822