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Implement 1W/1R with a transparent (or not) read port.
author
Cesar Strauss
<cestrauss@gmail.com>
Sun, 10 Apr 2022 12:24:19 +0000
(09:24 -0300)
committer
Cesar Strauss
<cestrauss@gmail.com>
Sun, 10 Apr 2022 12:24:19 +0000
(09:24 -0300)
Seems that it's just a matter of the underlying memories being
transparent (or not).
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