AddingPeripherals.mdwn

diff --git a/docs/AddingPeripherals.mdwn b/docs/AddingPeripherals.mdwn
index cbe2c306ff42a95f7f310bbd1ffb01e86b9f568f..e905a4a8c8043ad39cc79b9bfc147b76db70cc33 100644 (file)
--- a/docs/AddingPeripherals.mdwn
+++ b/docs/AddingPeripherals.mdwn
@@ -424,8 +424,7 @@ now they are to be connected *automatically* (on the peripheral side)
 to the IO pads in the pinmux.  However, at the time of writing this is
 not fully understood by the author, so the fastifdecl and extfastifinstance
 functions are modified to generate the correct output but the code is
-*commented out*, and the corresponding manual declarations of sdram_out
-removed.
+*commented out*
 
     def extfastifinstance(self, name, count):
         return "// TODO" + self._extifinstance(name, count, "_out", "", True,
@@ -435,6 +434,20 @@ removed.
         return "// (*always_ready*) interface " + \
                 "Ifc_sdram_out sdr{0}_out;".format(count)
 
+Also the corresponding (old) manual declarations of sdram\_out
+removed from the template:
+
+    `ifdef SDRAM                                            <-- xxxx
+        (*always_ready*) interface Ifc_sdram_out sdram_out; <-- xxxx
+    `endif                                                  <-- xxxx
+    ...
+    ...
+    `ifdef SDRAM                                  <--- xxxx
+        interface sdram_out=sdram.ifc_sdram_out;  <--- xxxx
+    `endif                                        <--- xxxx
+
+
+
 Next, again searching for signs of the "hand-written" code, we encounter
 the fabric connectivity, which wires the SDRAM to the AXI4.  We note however
 that there is not just one AXI slave device but *two*: one for the SDRAM

diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv
index 3d33f8edc95581c0d153e888dada5654eff8deb4..285ef0fad9475927e533f3fd13a55454740ad099 100644 (file)
--- a/src/bsv/bsv_lib/soc_template.bsv
+++ b/src/bsv/bsv_lib/soc_template.bsv
@@ -89,9 +89,6 @@ package socgen;
         (*always_ready,always_enabled*)
         method Action boot_sequence(Bit#(1) bootseq);
             
-        `ifdef SDRAM 
-            (*always_ready*) interface Ifc_sdram_out sdram_out; 
-        `endif
         `ifdef DDR
             (*prefix="M_AXI"*) interface
                    AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
@@ -299,9 +296,6 @@ package socgen;
         `endif 
          method Action boot_sequence(Bit#(1) bootseq) = 
                             core.boot_sequence(bootseq);
-        `ifdef SDRAM
-            interface sdram_out=sdram.ifc_sdram_out;
-        `endif
         `ifdef DDR
           interface master=fabric.v_to_slaves
                                 [fromInteger(valueOf(Sdram_slave_num))];