bug 1244: add linked list ddffirst image
[libreriscv.git] / HDL_workflow / ECP5_FPGA.mdwn
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2021-04-12 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:libreriscv
2021-04-11 Luke Kenneth Casso... restore colours back to originals to minimise changes.
2021-04-11 Luke Kenneth Casso... re-add removed images
2021-04-11 colepoirier@1ec9c8... (no commit message)
2021-04-11 Luke Kenneth Casso... add FT232 photo
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2021-04-11 colepoirierrestore ECP5_FPGA.mdwn, ft232r_jtag_wires.jpg, ulx3s_fp...
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2020-11-04 Luke Kenneth Casso... change to use 3.3v on VERSA X3
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2020-11-03 Luke Kenneth Casso... update jtag table, add colour to images
2020-11-03 Luke Kenneth Casso... add stlinkv2 photos
2020-11-03 Luke Kenneth Casso... swap wires around to match ulx3s
2020-11-03 Luke Kenneth Casso... format table
2020-11-03 Luke Kenneth Casso... add ECP5 JTAG connections
2020-11-03 Luke Kenneth Casso... add image links to ECP5 page
2020-11-03 Luke Kenneth Casso... add VERSA-ECP5 images, rename FPGA page