docs/firststeps: instruction execution
[libreriscv.git] / HDL_workflow /
2021-07-24 lkcl(no commit message)
2021-07-12 Luke Kenneth Casso... add note about reproduceability
2021-07-12 Luke Kenneth Casso... whitespace
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2021-05-24 R Veera KumarAdd pages for cocotb setup and use.
2021-05-24 R Veera KumarAdd pages for Icarus Verilog setup and use.
2021-05-24 R Veera KumarAdd pages for GHDL setup and use.
2021-05-22 lkcl(no commit message)
2021-05-22 lkcl(no commit message)
2021-05-20 R Veera KumarAdd pages for Verilator setup and use.
2021-05-09 Luke Kenneth Casso... include link to tasyagle
2021-04-12 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:libreriscv
2021-04-11 Luke Kenneth Casso... update DCD-FT232 image
2021-04-11 Luke Kenneth Casso... restore colours back to originals to minimise changes.
2021-04-11 Luke Kenneth Casso... re-add removed images
2021-04-11 colepoirier@1ec9c8... (no commit message)
2021-04-11 Luke Kenneth Casso... add FT232 photo
2021-04-11 Luke Kenneth Casso... add ft232 image
2021-04-11 colepoirier@1ec9c8... (no commit message)
2021-04-11 colepoirierrestore ECP5_FPGA.mdwn, ft232r_jtag_wires.jpg, ulx3s_fp...
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2021-04-10 colepoirierupdate rotation of ulx32 jtag wires image
2021-04-10 colepoirierupdate ft232r and ulx3s jtag wire images to reflect...
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2021-04-09 colepoirieradd new ft232 wiring colors images of ulx3s and ft232r...
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2021-03-29 Luke Kenneth Casso... update litex page
2021-03-29 Luke Kenneth Casso... add litex_ls180.mdwn
2021-03-29 mePy2placeholders
2021-03-29 mePy2corrections
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2021-03-28 mePy2correctly formatted the text.
2021-03-28 mePy2Populated the page with general git info and commands
2021-03-28 lkcl(no commit message)
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2021-03-10 R Veera KumarCorrections
2021-03-10 R Veera KumarCorrections
2021-03-10 R Veera KumarInstallation instructions for nextpnr with ECP5
2021-03-09 colepoirier@1ec9c8... (no commit message)
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2020-11-23 lkcl(no commit message)
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2020-11-04 Luke Kenneth Casso... show tab on imag
2020-11-04 Luke Kenneth Casso... update FPGA connector images
2020-11-04 Luke Kenneth Casso... change to use 3.3v on VERSA X3
2020-11-04 colepoirier@1ec9c8... (no commit message)
2020-11-04 Cole PoirierHDL_wokflow update ulx3s jtag jumper wire connection...
2020-11-04 Cole PoirierHDL_workflow/ECP5_FPGA provide two images showing diffe...
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2020-11-04 Cole Poirierupdate photo for stlinkv2 JTAG wires in HDL_Workflow...
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2020-11-03 Luke Kenneth Casso... colour-mark X3 VERSA ECP5 JTAG pins
2020-11-03 Luke Kenneth Casso... update jtag table, add colour to images
2020-11-03 Luke Kenneth Casso... add stlinkv2 photos
2020-11-03 Luke Kenneth Casso... add stlinkv2 connector images
2020-11-03 Luke Kenneth Casso... swap wires around to match ulx3s
2020-11-03 Luke Kenneth Casso... format table
2020-11-03 Luke Kenneth Casso... add ECP5 JTAG connections
2020-11-03 Luke Kenneth Casso... add image links to ECP5 page
2020-11-03 Luke Kenneth Casso... add versa ecp5 x3 photo
2020-11-03 Luke Kenneth Casso... add VERSA-ECP5 images, rename FPGA page
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