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Factor out the dummy RoCC accelerator
[riscv-isa-sim.git]
/
hwacha
/
hwacha.mk.in
2014-11-25
Andrew Waterman
Factor out the dummy RoCC accelerator
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2014-07-07
Andrew Waterman
Use precompiled headers to speed up compilation
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2014-02-04
Quan Nguyen
Move half precision instructions, add vfmsv, vfmvv
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2014-01-21
Quan Nguyen
Merge branch 'confprec'
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2013-11-25
Andrew Waterman
Update to new privileged ISA
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2013-11-25
Quan Nguyen
Merge branch 'master' of github.com:ucb-bar/riscv-isa...
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2013-11-05
Albert Ou
Fix declaration of half-precision instructions
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2013-11-05
Albert Ou
Re-add Hwacha header file
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2013-11-05
Albert Ou
Implement "half-baked" half-precision instruction subse...
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2013-11-05
Albert Ou
Merge branch 'master' of github.com:ucb-bar/riscv-isa...
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2013-10-19
Yunsup Lee
refactor disassembler, and add hwacha disassembler
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2013-10-16
Yunsup Lee
revamp hwacha; now runs in physical mode
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