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Update README.md for freg info
[riscv-isa-sim.git] / hwacha / insns_ut /
2015-03-13 Andrew WatermanUpdate to new privileged spec tree | commitdiff
2014-04-03 Stephen TwiggMerge branch 'tm' tree | commitdiff
2014-04-03 Stephen TwiggAdd ut_fclass_s/d hwacha (unused until encoding sync) tree | commitdiff
2014-02-04 Quan NguyenMove half precision instructions, add vfmsv, vfmvv tree | commitdiff
2013-11-05 Albert OuMerge branch 'master' of github.com:ucb-bar/riscv-isa... tree | commitdiff
2013-10-18 Yunsup Leecan't execute frsr/fssr on ut tree | commitdiff
2013-10-16 Yunsup Leerevamp hwacha; now runs in physical mode tree | commitdiff
Simple-V augmented version of spike